Name
Title | ||
|---|---|---|
A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. |
Abstract | ||
|---|---|---|
This paper presents circuit techniques to reduce both active and standby mode power, especially at room temperature (RT). A bit-line power calculator is used to adaptively set the cell supply voltage (V-CS) in the active mode. A digitally controllable retention circuit regulates V-CS in the standby mode with small control power. These circuits are implemented in a dual-power-supply SRAM in 28-nm CMOS technology. Compared with the conventional scheme, the power consumption in the active and standby mode at 25 degrees C is reduced by 27% and 85%, respectively. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/JSSC.2013.2280312 | J. Solid-State Circuits |
Keywords | DocType | Volume |
Bit-line power, digital control, low power, replica BL, retention circuit, SRAM | Journal | 49 |
Issue | ISSN | ISBN |
1 | 0018-9200 | 978-1-4673-4515-6 |
Citations | PageRank | References |
3 | 0.40 | 6 |
Authors | ||
11 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fumihiko Tachibana | 1 | 37 | 5.98 |
| Osamu Hirabayashi | 2 | 76 | 10.08 |
| Yasuhisa Takeyama | 3 | 86 | 11.06 |
| Miyako Shizuno | 4 | 5 | 1.15 |
| Atsushi Kawasumi | 5 | 153 | 19.91 |
| Keiichi Kushida | 6 | 71 | 10.19 |
| atsushi suzuki | 7 | 63 | 8.55 |
| Yusuke Niki | 8 | 44 | 5.58 |
| Shin-ichi Sasaki | 9 | 160 | 44.66 |
| Tomoaki Yabe | 10 | 86 | 11.09 |
| Yasuo Unekawa | 11 | 32 | 5.89 |