| A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. | 3 | 0.40 | 2014 |
| 19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension | 1 | 0.38 | 2014 |
| 4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control | 3 | 0.62 | 2014 |
| A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJetTM SoC in 65 nm CMOS. | 1 | 0.36 | 2013 |
| A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. | 5 | 0.76 | 2013 |
| A-70 Dbm-Sensitivity 522 Mbps 0.19 Nj/Bit-Tx 0.43 Nj/Bit-Rx Transceiver For Transferjet (Tm) Soc In 65 Nm Cmos | 0 | 0.34 | 2013 |
| A Standard-Cell Based On-Chip Nmos And Pmos Performance Monitor For Process Variability Compensation | 0 | 0.34 | 2013 |
| A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit. | 1 | 0.35 | 2013 |
| A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. | 5 | 0.63 | 2012 |
| An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation | 3 | 0.44 | 2012 |
| A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor | 1 | 0.38 | 2011 |
| A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications | 0 | 0.34 | 2011 |
| High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors | 9 | 0.54 | 2011 |
