Name
Abstract | ||
|---|---|---|
In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, where the output logic level changes L to H by applying a test input vector to a circuit under test. The technique is applied to built-in IDDQ sensor design and external IDDQ sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ATS.2001.990268 | Asian Test Symposium |
Keywords | DocType | ISSN |
high speed tests,built-in iddq sensor design,integrated circuit testing,sensor design,load capacitors,high speed iddq test,test input vector,IDDQ sensing technique,high speed,CMOS logic gates,load capacitor,high speed IDDQ testing,high-speed integrated circuits,useful technique,CMOS logic circuits,cmos logic gate,output logic level,external iddq sensor design,automatic testing,iddq testing,logic gates,iddq sensing technique,circuit under test,logic testing | Conference | 1081-7735 |
ISBN | Citations | PageRank |
0-7695-1378-6 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Teppei Takeda | 1 | 1 | 0.70 |
| Masaki Hashizume | 2 | 98 | 27.83 |
| Masahiro Ichimiya | 3 | 4 | 2.36 |
| Hiroyuki Yotsuyanagi | 4 | 70 | 19.04 |
| Yukiya Miura | 5 | 83 | 15.06 |
| Kozo Kinoshita | 6 | 756 | 118.08 |