Name
Title | ||
|---|---|---|
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs |
Abstract | ||
|---|---|---|
Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on the circuit level. We first provide parasitic RC characteristics of intertier connections including TSV and microbumps and examine their delay. Then circuit simulation is performed to evaluate the timing impact of intertier connections. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TVLSI.2010.2090049 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
intertier connections,circuit level,deep submicron design,3-d ics,timing impact,electrical characterization,intertier connection,parasitic rc characteristic,3-d technology,major concern,timing analysis,vertical intertier connection,circuit simulation,integrated circuit,metals,through silicon via,process variation,capacitance,integrated circuit design | Capacitance,Computer science,Electronic engineering,Integrated circuit design,Through-silicon via,Static timing analysis,Interconnection,Electrical engineering,Power consumption | Journal |
Volume | Issue | ISSN |
20 | 1 | 1063-8210 |
Citations | PageRank | References |
15 | 0.95 | 5 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaoxia Wu | 1 | 535 | 38.61 |
| Wei Zhao | 2 | 15 | 0.95 |
| Mark Nakamoto | 3 | 16 | 1.39 |
| Chandra Nimmagadda | 4 | 15 | 0.95 |
| Durodami Lisk | 5 | 15 | 0.95 |
| Sam Gu | 6 | 15 | 0.95 |
| Riko Radojcic | 7 | 31 | 4.68 |
| Matt Nowak | 8 | 51 | 4.99 |
| Yuan Xie | 9 | 6430 | 407.00 |