Xiaoxia Wu - Citegraph

Author Info

Name	Affiliation	Papers
XIAOXIA WU	Zhongnan Univ Econ & Law, Wuhan Coll, Wuhan, Hubei, Peoples R China	25
Collaborators	Citations	PageRank
89	535	38.61
Referers	Referees	References
1192	599	243

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Publications (25 rows)

Collaborators (89 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
On structural properties of -minimal chemical trees.	0	0.34	2019
Spanning trees and recurrent configurations of a graph.	0	0.34	2017
Height Probabilities in the Abelian Sandpile Model on the Generalized Trees.	0	0.34	2014
A 130.7-Mm(2) 2-Layer 32-Gb Reram Memory Device In 24-Nm Technology	20	2.52	2014
A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology	0	0.34	2013
Small Randic Index Ordering of Trees with k Pendant Vertices.	0	0.34	2012
Estimating the Proportion of True Null Hypotheses in Nonparametric Exponential Mixture Model with Appication to the Leukemia Gene Expression Data.	0	0.34	2012
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs	15	0.95	2012
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation.	4	0.44	2011
Test-access mechanism optimization for core-based three-dimensional SOCs	24	1.85	2010
Design exploration of hybrid caches with disparate memory technologies	8	1.13	2010
Power and performance of read-write aware Hybrid Caches with non-volatile memories	61	2.96	2009
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control	10	0.57	2009
Scan-chain design and optimization for three-dimensional integrated circuits	20	1.42	2009
Variability-driven module selection with joint design time optimization and post-silicon tuning	28	1.00	2008
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement	173	12.18	2008
Individual patient diagnosis of AD and FTD via high-dimensional pattern classification of MRI.	47	3.06	2008
Test-Access Solutions for Three-Dimensional SOCs	1	0.61	2008
Scan chain design for three-dimensional integrated circuits (3D ICs)	30	2.16	2007
On-chip bus thermal analysis and optimisation	0	0.34	2007
Variation-aware task allocation and scheduling for MPSoC	45	1.54	2007
Guaranteeing performance yield in high-level synthesis	27	1.07	2006
Analysis Of Subthreshold Finfet Circuits For Ultra-Low Power Design	7	0.79	2006
On Concatenated Zigzag Codes and Their Decoding Schemes	3	0.43	2004
Membership function modification of fuzzy logic controllers with histogram equalization.	12	1.56	2001