Name
Abstract | ||
|---|---|---|
A recent approach is capable of identifying threshold logic functions with as many as fifty inputs with small integer weights on the inputs. An analytical method is presented for selecting optimum sensor sizes. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Exhaustive SPICE simulations show that implemented TLGs by the proposed approach consistently exhibit behavior very close to the optimal. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISVLSI.2012.34 | ISVLSI |
Keywords | Field | DocType |
CMOS logic circuits,delays,logic gates,CMOS gates,delay analysis method,exhaustive SPICE simulations,n-input current mode threshold logic gate,small integer weights,threshold logic functions,Threshold logic gates,current mode,operating speed,sensor sizing | Delay calculation,Topology,Logic gate,Sequential logic,Pass transistor logic,High Threshold Logic,Computer science,AND-OR-Invert,Programmable logic array,Electronic engineering,Logic family | Conference |
Citations | PageRank | References |
6 | 0.67 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chandra Babu Dara | 1 | 13 | 2.01 |
| Themistoklis Haniotakis | 2 | 97 | 16.09 |
| Spyros Tragoudas | 3 | 625 | 88.87 |