Paper Info
Title
Functional test pattern generation for maximizing temperature in 3D IC chip stack
Abstract
In a stacked 3D Integrated Circuit (IC), the total power dissipated per unit surface area typically exceeds that of 2D ICs. This results in creation of a greater number of localized thermal hotspots in individual dies of the 3D IC. The location and temperature of these hotspots depend on the actual workload executing on a 3D IC. Since the power dissipation pattern from the applied workload may vary over time, the location and intensity of thermal hotspots may vary with it. The applied workload may be construed as consisting of phases, where the spatial power dissipation pattern remains constant over a phase and changes only from one phase to another. In this paper (i) we develop a thermal modeling scheme that predicts temperature profile at the end of a program phase, and use (ii) a novel Integer Linear Programming (ILP) formulation to arrange program phases to create worst case temperature at a target location. Experimental results show that, by taking the spatio-temporal effect into account, we can raise temperature of a hotspot much higher than what is possible from purely functional trace. Hotspot temperature maximization is important in design verification and testing.
Year
DOI
Venue
2012
10.1109/ISQED.2012.6187482
ISQED
Keywords
Field
DocType
stacked 3d integrated circuit,functional test pattern generation,packaging,3d ic chip stack,integrated circuit testing,design verification,program phase,ilp formulation,wavelet transforms,total power dissipation pattern,design testing,three-dimensional integrated circuits,integer programming,thermal hotspot,circuit optimisation,worst case temperature,thermal simulation,linear programming,integer linear programming,spatial power dissipation pattern,wavelet tranform,integrated circuit design,thermal modeling,integer linear programming (ilp),integrated circuit packaging,wavelet transform,hotspot temperature maximization,3d ic,spatio-temporal effect,temperature profile,power dissipation,thermal resistance,surface area,functional testing,chip,heat sinks
Computer science,Dissipation,Integrated circuit packaging,Electronic engineering,Real-time computing,Chip,Integrated circuit design,Integer programming,Three-dimensional integrated circuit,Heat sink,Thermal resistance
Conference
ISSN
ISBN
Citations 
1948-3287
978-1-4673-1034-5
2
PageRank 
References 
Authors
0.36
7
2
Name
Order
Citations
PageRank
Sudarshan Srinivasan1335.01
Sandip Kundu21103137.18