| Hardening DNNs against Transfer Attacks during Network Compression using Greedy Adversarial Pruning | 0 | 0.34 | 2022 |
| Weightless Neural Networks as Memory Segmented Bloom Filters | 2 | 0.38 | 2020 |
| Building a portable deeply-nested implicit information flow tracking | 0 | 0.34 | 2020 |
| Reliability Evaluation of Compressed Deep Learning Models | 2 | 0.39 | 2020 |
| Hardware-Accelerated Similarity Search With Multi-Index Hashing | 0 | 0.34 | 2019 |
| MPP Keynote 1 | 0 | 0.34 | 2019 |
| MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems | 0 | 0.34 | 2019 |
| Efficient Testing of Physically Unclonable Functions for Uniqueness | 0 | 0.34 | 2019 |
| Remote Configuration of Integrated Circuit Features and Firmware Management via Smart Contract | 2 | 0.39 | 2019 |
| On IC traceability via blockchain | 0 | 0.34 | 2018 |
| Poster Abstract: Privacy in Blockchain-Enabled IoT Devices | 1 | 0.38 | 2018 |
| Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions. | 2 | 0.37 | 2017 |
| Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. | 0 | 0.34 | 2016 |
| An Efficient Method For Clock Skew Scheduling To Reduce Peak Current | 2 | 0.40 | 2016 |
| Abstraction-Guided Simulation Using Markov Analysis for Functional Verification | 1 | 0.36 | 2016 |
| Managing reliability of integrated circuits: Lifetime metering and design for healing | 0 | 0.34 | 2016 |
| Modeling Residual Life of an IC Considering Multiple Aging Mechanisms | 0 | 0.34 | 2016 |
| Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification | 0 | 0.34 | 2016 |
| A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics | 16 | 0.73 | 2015 |
| A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors | 0 | 0.34 | 2015 |
| Guest Editorial: Special Section on Circuit and System Design Methodologies for Emerging Technologies | 0 | 0.34 | 2015 |
| A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency | 2 | 0.39 | 2014 |
| A Chaotic Ring oscillator based Random Number Generator | 7 | 0.73 | 2014 |
| Domino effect protection on dataflow error detection and recovery. | 0 | 0.34 | 2014 |
| A low-power instruction replay mechanism for design of resilient microprocessors | 2 | 0.41 | 2014 |
| Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip | 0 | 0.34 | 2014 |
| Online error detection and recovery in dataflow execution | 2 | 0.41 | 2014 |
| Glitch Power Reduction via Clock Skew Scheduling | 2 | 0.42 | 2014 |
| On pattern generation for maximizing IR drop | 2 | 0.64 | 2014 |
| Performance-driven dynamic thermal management of MPSoC based on task rescheduling | 2 | 0.36 | 2014 |
| On dynamic polymorphing of a superscalar core for improving energy efficiency | 0 | 0.34 | 2013 |
| Synchronizing Differential Evolution with a modified affinity-based mutation framework | 3 | 0.39 | 2013 |
| A study on polymorphing superscalar processor dynamically to improve power efficiency | 1 | 0.34 | 2013 |
| Program phase duration prediction and its application to fine-grain power management | 3 | 0.41 | 2013 |
| A system-level solution for managing spatial temperature gradients in thinned 3D ICs | 2 | 0.39 | 2013 |
| An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs | 12 | 0.64 | 2013 |
| A study of tapered 3-D TSVs for power and thermal integrity | 25 | 1.52 | 2013 |
| Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency | 11 | 0.54 | 2012 |
| A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays | 1 | 0.38 | 2012 |
| Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes | 3 | 0.39 | 2012 |
| Functional test pattern generation for maximizing temperature in 3D IC chip stack | 2 | 0.36 | 2012 |
| Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime. | 0 | 0.34 | 2012 |
| A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip | 2 | 0.40 | 2012 |
| On lithography aware metal-fill insertion | 1 | 0.36 | 2012 |
| Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt | 4 | 0.43 | 2012 |
| On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs | 0 | 0.34 | 2012 |
| On Reliability Trojan Injection And Detection | 4 | 0.43 | 2012 |
| Efficient BDD-based Fault Simulation in Presence of Unknown Values | 2 | 0.40 | 2011 |
| Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits | 0 | 0.34 | 2011 |
| An Architecture to Enable Life Cycle Testing in CMPs | 4 | 0.42 | 2011 |
