Title
A Hardware Architecture For Accelerating Neuromorphic Vision Algorithms
Abstract
Neuromorphic vision algorithms are biologically inspired algorithms that follow the processing that takes place in the visual cortex. These algorithms have proved to match classical computer vision algorithms in classification performance and even outperformed them in some instances. However, neuromorphic algorithms suffer from high complexity leading to poor execution times when running on general purpose processors, making them less attractive for real-time applications. FPGAs, on the other hand, have become true signal processing platforms due to their lightweight, low power consumption and massive parallel computational resources. This paper describes an FPGA-based hardware architecture that accelerates an object classification cortical model, HMAX. Compared to a CPU implementation, this hardware accelerator offers 23X (89X) speedup when mapped to a single-FPGA (multi-FPGA) platform, while maintaining a classification accuracy of 92.5%.
Year
DOI
Venue
2011
10.1109/SiPS.2011.6089002
2011 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS)
Keywords
Field
DocType
Neuromorphic vision algorithms, FPGA, Signal Processing, Hardware, Neuromorphic Hardware Architecture
Kernel (linear algebra),Signal processing,Computer science,Parallel computing,Neuromorphic engineering,Field-programmable gate array,Hardware acceleration,Contextual image classification,Hardware architecture,Speedup
Conference
ISSN
Citations 
PageRank 
1520-6130
7
0.59
References 
Authors
4
5
Name
Order
Citations
PageRank
Ahmed Al Maashri1958.62
Michael Debole21249.87
Chi-Li Yu3395.45
Narayanan Vijaykrishnan46955524.60
Chaitali Chakrabarti51978184.17