| Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks | 1 | 0.36 | 2022 |
| An Adjustable Farthest Point Sampling Method for Approximately-sorted Point Cloud Data | 0 | 0.34 | 2022 |
| LiDAR-Aided Mobile Blockage Prediction in Real-World Millimeter Wave Systems | 0 | 0.34 | 2022 |
| Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory | 0 | 0.34 | 2022 |
| ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning | 0 | 0.34 | 2022 |
| Deep Learning for Moving Blockage Prediction using Real mmWave Measurements | 0 | 0.34 | 2022 |
| Blockage Prediction Using Wireless Signatures: Deep Learning Enables Real-World Demonstration | 0 | 0.34 | 2022 |
| T-BFA: <underline>T</underline>argeted <underline>B</underline>it-<underline>F</underline>lip Adversarial Weight <underline>A</underline>ttack | 2 | 0.41 | 2022 |
| Communication and Computation Reduction for Split Learning using Asynchronous Training | 1 | 0.36 | 2021 |
| Defending Bit-Flip Attack Through Dnn Weight Reconstruction | 0 | 0.34 | 2020 |
| A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs | 3 | 0.40 | 2020 |
| A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. | 2 | 0.37 | 2020 |
| A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors. | 5 | 0.42 | 2019 |
| MAX2: An ReRAM-based Neural Network Accelerator that Maximizes Data Reuse and Area Utilization | 0 | 0.34 | 2019 |
| Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications | 0 | 0.34 | 2019 |
| Articulation constrained learning with application to speech emotion recognition | 0 | 0.34 | 2019 |
| A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm | 0 | 0.34 | 2019 |
| OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator | 17 | 0.55 | 2018 |
| A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks | 1 | 0.35 | 2018 |
| A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware. | 0 | 0.34 | 2018 |
| Reducing Energy of Baseband Processor for IoT Terminals with Long Range Wireless Communications | 0 | 0.34 | 2018 |
| Parallel Wavelet-based Bayesian Compressive Sensing based on Gibbs Sampling | 0 | 0.34 | 2018 |
| Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. | 2 | 0.36 | 2017 |
| Low Complexity 3D Ultrasound Imaging Using Synthetic Aperture Sequential Beamforming | 0 | 0.34 | 2016 |
| Low Power Baseband Processor For Iot Terminals With Long Range Wireless Communications | 0 | 0.34 | 2016 |
| Checkpointing Exascale Memory Systems with Existing Memory Technologies. | 3 | 0.49 | 2016 |
| Within and cross-corpus speech emotion recognition using latent topic model-based features. | 9 | 0.50 | 2015 |
| Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings | 7 | 0.48 | 2015 |
| Programming strategies to improve energy efficiency and reliability of ReRAM memory systems | 3 | 0.44 | 2015 |
| Separable Beamforming For 3-D Medical Ultrasound Imaging | 4 | 0.58 | 2015 |
| Low cost clutter filter for 3D ultrasonic flow estimation | 0 | 0.34 | 2015 |
| A multi-modal approach to emotion recognition using undirected topic models | 3 | 0.44 | 2014 |
| A low complexity scheme for accurate 3D velocity estimation in ultrasound systems | 1 | 0.43 | 2014 |
| Sonic Millip3De: An Architecture for Handheld 3D Ultrasound | 1 | 0.56 | 2014 |
| A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram | 3 | 0.47 | 2014 |
| Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding | 2 | 0.44 | 2014 |
| Parallelization techniques for implementing trellis algorithms on graphics processors | 2 | 0.53 | 2013 |
| A speech emotion recognition framework based on latent Dirichlet allocation: Algorithm and FPGA implementation | 6 | 0.47 | 2013 |
| An analytical approach to efficient circuit variability analysis in scaled CMOS design | 5 | 0.60 | 2012 |
| Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell PRAM | 3 | 0.44 | 2012 |
| A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS | 24 | 1.41 | 2012 |
| Reducing the Complexity of Orthogonal Code Based Synthetic Aperture Ultrasound System | 0 | 0.34 | 2012 |
| Product code schemes for error correction in MLC NAND flash memories | 26 | 1.51 | 2012 |
| A top-down design methodology using virtual platforms for concept development. | 3 | 0.41 | 2012 |
| Neural activity tracking using spatial compressive particle filtering | 1 | 0.43 | 2012 |
| Transpose-Free Sar Imaging On Fpga Platform | 4 | 0.49 | 2012 |
| FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data | 1 | 0.43 | 2011 |
| Algorithm and Parallel Implementation of Particle Filtering and its Use in Waveform-Agile Sensing | 7 | 0.55 | 2011 |
| Accurate Area, Time and Power Models for FPGA-Based Implementations | 14 | 0.89 | 2011 |
| Multidimensional DFT IP Generator for FPGA Platforms | 14 | 1.11 | 2011 |
