Name
Abstract | ||
|---|---|---|
This paper explores the possibility of enabling a partial customisability of the Instruction Set of Very Long Instruction Wold processors for embedded applications, by exploiting Field Programmable Gate Arrays technology. A formal methodology is presented leading to selection of the application critical ports, whose RFUs (Reconfigurable Functional Units) implementation allows the reduction of overall execution time. Experiments performed on representative benchmarks show the applicability of the proposed approach. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1145/307418.307504 | DATE |
Keywords | Field | DocType |
reconfigurable vliw processor,dag-based design approach | Computer architecture,Computer science,Very long instruction word,Parallel computing,Real-time computing | Conference |
ISBN | Citations | PageRank |
1-58113-121-6 | 35 | 3.13 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cesare Alippi | 1 | 1040 | 115.84 |
| William Fornaciari | 2 | 543 | 67.45 |
| Laura Pozzi | 3 | 35 | 3.13 |
| Mariagiovanna Sami | 4 | 314 | 39.98 |