| Embedded Systems Education: Job Market Expectations. | 0 | 0.34 | 2016 |
| Fault-Tolerant Network Interfaces for Networks-on-Chip | 1 | 0.38 | 2014 |
| A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project | 7 | 0.48 | 2013 |
| An OpenCL-based feature matcher | 3 | 0.44 | 2013 |
| System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach | 11 | 0.60 | 2012 |
| Design of Fault Tolerant Network Interfaces for NoCs | 5 | 0.45 | 2011 |
| ADSC: application-driven storage control for energy efficiency | 1 | 0.36 | 2011 |
| Analyzing the Sensitivity to Faults of Synchronization Primitives | 0 | 0.34 | 2011 |
| Creating an embedded systems program from scratch: nine years of experience at ALaRI | 1 | 0.41 | 2009 |
| Power Modeling and Power Analysis for IEEE 802.15.4: a Concurrent State Machine Approach | 8 | 0.65 | 2007 |
| Self-adaptive Security at Application Level: a Proposal | 3 | 0.47 | 2007 |
| Security Aspects in Networks-on-Chips: Overview and Proposals for Secure Implementations | 18 | 1.23 | 2007 |
| Flexible Power Modeling for Wireless Systems: Power Modeling and Optimization of two Bluetooth Implementations | 7 | 0.73 | 2005 |
| Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications | 5 | 0.43 | 2005 |
| Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor | 0 | 0.34 | 2005 |
| FSM--based power modeling of wireless protocols: the case of bluetooth | 13 | 1.20 | 2004 |
| Embedded systems education: how to teach the required skills? | 4 | 0.57 | 2004 |
| Fault-tolerant CAM architectures: a design framework | 4 | 0.41 | 2002 |
| On-line Diagnosis and Reconfiguration of FPGA Systems | 8 | 1.39 | 2002 |
| SIMD extension to VLIW multicluster processors for embedded applications | 3 | 0.41 | 2002 |
| Semiconcurrent error detection in data paths | 16 | 1.34 | 2001 |
| A DAG-based design approach for reconfigurable VLIW processors | 35 | 3.13 | 1999 |
| Co-Testing: Granting Testability in a Codesign Environment | 0 | 0.34 | 1998 |
| High-level synthesis of data paths with concurrent error detection | 20 | 1.72 | 1998 |
| Array partitioning to achieve defect tolerance | 0 | 0.34 | 1997 |
| Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays | 2 | 0.40 | 1997 |
| Semi-concurrent error detection in data paths | 6 | 0.74 | 1997 |
| Harvesting through array partitioning: a solution to achieve defect tolerance | 7 | 0.77 | 1997 |
| Context reorder buffer: an architectural support for real-time processing on RISC architectures | 1 | 0.38 | 1996 |
| Testability of artificial neural networks: a behavioral approach | 3 | 0.50 | 1995 |
| The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings | 43 | 8.56 | 1993 |
| A behavioral approach to testability analysis for neural networks | 1 | 0.40 | 1992 |
| Testing and diagnosis ofFFT arrays | 3 | 0.48 | 1991 |
| Fault Tolerance Fechniques for Array Structures Used in Supercomputing | 7 | 0.74 | 1986 |
| Fault-tolerance in parallel architectures | 0 | 0.34 | 1986 |
| Reconfigurable architectures for VLSI processing arrays | 68 | 8.19 | 1983 |
