Name
Title | ||
|---|---|---|
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. |
Abstract | ||
|---|---|---|
This paper presents a self-testing and calibration technique for the embedded successive approximation register (SAR) analog-to-digital converter (ADC) in system-on-chip (SoC) designs. We first proposed a low cost design-for-test (DfT) technique that estimates the SAR ADC performance before and after calibration by characterizing its digital-to-analog converter (DAC) capacitor weights (bit weights). Utilizing major carrier transition (MCT) testing, the required analog measurement range is only about 1 LSB; this significantly reduces test circuitry complexity. Then, we develop a fully-digital calibration technique that utilizes the extracted bit weights to correct the non-ideal I/O behavior induced by capacitor mismatch. Simulation results show that (1) the proposed testing technique achieves very high test accuracy even in the presence of large noise, and (2) the proposed calibration technique effectively improves both static and dynamic performances of the SAR ADC. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1007/s10836-012-5325-0 | J. Electronic Testing |
Keywords | Field | DocType |
Successive approximation register ADC,ADC testing,ADC calibration,Capacitor mismatch,Major-carrier transition testing | Capacitor,Computer science,Shaping,Real-time computing,Electronic engineering,Successive approximation ADC,Calibration,Least significant bit | Journal |
Volume | Issue | ISSN |
28 | 5 | 0923-8174 |
Citations | PageRank | References |
3 | 0.58 | 10 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xuan-Lun Huang | 1 | 23 | 5.33 |
| Jiun-Lang Huang | 2 | 263 | 35.90 |
| Hung-I Chen | 3 | 3 | 0.58 |
| Chang-Yu Chen | 4 | 25 | 217.76 |
| Tseng Kuo-Tsai | 5 | 3 | 0.58 |
| Ming-Feng Huang | 6 | 3 | 0.58 |
| Yung-Fa Chou | 7 | 244 | 23.76 |
| Ding-Ming Kwai | 8 | 521 | 46.85 |