| Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method | 0 | 0.34 | 2020 |
| RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction | 1 | 0.37 | 2018 |
| A channel-sharable built-in self-test scheme for multi-channel DRAMs. | 0 | 0.34 | 2018 |
| Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs | 1 | 0.38 | 2017 |
| On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC | 1 | 0.36 | 2017 |
| Hierarchical Test Integration Methodology for 3D ICs | 0 | 0.34 | 2015 |
| Temperature-aware online testing of power-delivery TSVs | 0 | 0.34 | 2015 |
| A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs | 1 | 0.36 | 2015 |
| A hybrid built-in self-test scheme for DRAMs | 3 | 0.40 | 2015 |
| BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs | 0 | 0.34 | 2014 |
| A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage | 4 | 0.43 | 2014 |
| Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults | 3 | 0.44 | 2014 |
| Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs | 1 | 0.35 | 2014 |
| In-situ method for TSV delay testing and characterization using input sensitivity analysis | 12 | 0.75 | 2013 |
| Die-To-Die Clock Synchronization For 3-D Ic Using Dual Locking Mechanism | 0 | 0.34 | 2013 |
| Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis | 13 | 0.80 | 2013 |
| Worst-case IR-drop monitoring with 1GHz sampling rate | 1 | 0.38 | 2013 |
| Enabling inter-die co-optimization in 3-D IC with TSVs | 0 | 0.34 | 2013 |
| An FPGA-based test platform for analyzing data retention time distribution of DRAMs | 7 | 0.50 | 2013 |
| A hybrid ECC and redundancy technique for reducing refresh power of DRAMs | 0 | 0.34 | 2013 |
| Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. | 5 | 0.50 | 2013 |
| I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs | 2 | 0.41 | 2013 |
| An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. | 3 | 0.58 | 2012 |
| A built-in self-test scheme for 3D RAMs | 1 | 0.37 | 2012 |
| Small delay testing for TSVs in 3-D ICs | 19 | 0.83 | 2012 |
| 3-D centric technology and realization with TSV | 0 | 0.34 | 2012 |
| A self-testing and calibration method for embedded successive approximation register ADC | 5 | 0.56 | 2011 |
| A built-in self-test scheme for the post-bond test of TSVs in 3D ICs | 31 | 1.45 | 2011 |
| A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager | 2 | 0.44 | 2011 |
| Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias | 12 | 0.72 | 2011 |
| Performance Characterization of TSV in 3D IC via Sensitivity Analysis | 34 | 1.71 | 2010 |
| A Test Integration Methodology for 3D Integrated Circuits | 9 | 0.66 | 2010 |
| CAD reference flow for 3D via-last integrated circuits | 5 | 0.64 | 2010 |
| Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms | 16 | 1.18 | 2007 |
| SRAM cell current in low leakage design | 1 | 0.40 | 2006 |
| FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment | 0 | 0.34 | 2006 |
| SRAM delay fault modeling and test algorithm development | 4 | 0.48 | 2004 |
| Defect oriented fault analysis for SRAM | 11 | 0.78 | 2003 |
| FAME: A Fault-Pattern Based Memory Failure Analysis Framework | 8 | 0.62 | 2003 |
| Flash memory built-in self-test using March-like algorithms | 25 | 1.67 | 2002 |
| etection of SRAM cell stability by lowering array supply voltage | 3 | 0.87 | 2000 |
