Name
Abstract | ||
|---|---|---|
This paper introduces a low overhead test methodology, RT-SCAN, applicable to RT Level designs. The methodology enables using combinational test patterns for testing the circuit, as done by traditional full-scan or parallel-scan schemes. However, by exploiting existing connectivity of registers through multiplexors and functional units, RT-SCAN reduces area overhead and test application times significantly compared to full-scan and parallel-scan schemes. Unlike most of the existing high-level test synthesis and test generation schemes which can be most effectively applied to data-flow/arithmetic intensive designs like DSPs and processor designs, the RT-SCAN test scheme can be applied to designs from any application domain, including control-flow intensive designs. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/EDTC.1997.582349 | ED&TC |
Keywords | Field | DocType |
automatic testing,combinational circuits,high level synthesis,logic testing,ATPG tool,RT-SCAN,RTL methodology,application time,area overhead,combinational testing,functional unit,high-level test synthesis,multiplexor,register connectivity | Test method,Test synthesis,Logic testing,Computer science,High-level synthesis,Automatic testing,Multiplexer,Real-time computing,Combinational logic,Application domain | Conference |
ISSN | ISBN | Citations |
1066-1409 | 0-8186-7786-4 | 3 |
PageRank | References | Authors |
0.57 | 15 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Subhrajit Bhattacharya | 1 | 462 | 36.93 |
| Sujit Dey | 2 | 3067 | 278.74 |
| Bhaskar Sengupta | 3 | 369 | 55.47 |