Paper Info
Title
Power-Aware Multi-Frequency Heterogeneous Soc Test Framework Design With Floor-Ceiling Packing
Abstract
This paper presents a solution to the multi-frequency heterogeneous SoC test integration and reuse, which is considered the major hurdle of SoC manufacturing capability, and thus is the key component of SoC test automation. A hybrid system level test framework is designed and optimized to tackle heterogeneous test environment with the combination of BIST and the external test. Several interdependent design items including test access mechanism design, bandwidth matching, multi-frequency interface configuration, and test scheduling under tight power and pin count limitation, are well studies and incorporated into the test framework. The trade-off between test time, test power and bandwidth is well balanced to achieve the minimum test cost in terms of test time and test interface. The simulation study shows the promising results of the proposed floor-ceiling packing approach.
Year
DOI
Venue
2007
10.1109/ISCAS.2007.377866
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11
Keywords
Field
DocType
integrated circuit design,system testing,engines,job shop scheduling,hybrid system,frequency,system on chip,bandwidth
Automatic test pattern generation,System on a chip,Job shop scheduling,Computer science,System testing,Electronic engineering,Integrated circuit design,Bandwidth (signal processing),Hybrid system,Built-in self-test,Embedded system
Conference
ISSN
Citations 
PageRank 
0271-4302
2
0.36
References 
Authors
4
4
Name
Order
Citations
PageRank
Dan Zhao118815.29
Ronghua Huang220.70
Tomokazu Yoneda315419.35
Hideo Fujiwara4343.55