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HIDEO FUJIWARA
Author Info
Open Visualization
Name
Affiliation
Papers
HIDEO FUJIWARA
Nara Inst Sci & Technol, Grad Sch Informat Sci, Nara, Japan
8
Collaborators
Citations
PageRank
14
34
3.55
Referers
Referees
References
95
252
130
Search Limit
100
252
Publications (8 rows)
Collaborators (14 rows)
Referers (95 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip.
10
0.44
2016
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage
6
0.58
2010
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips
0
0.34
2008
TAM Design and Optimization for Transparency-Based SoC Test
1
0.36
2007
Power-Aware Multi-Frequency Heterogeneous Soc Test Framework Design With Floor-Ceiling Packing
2
0.36
2007
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints
3
0.44
2007
Power-constrained test scheduling for multi-clock domain SoCs
10
0.64
2006
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability
2
0.39
2005
1