Name
Abstract | ||
|---|---|---|
High performance implementation of 2D digital filters are highly desired in many applications for real-time processing. In this paper, a multiprocessor realization of a 2D denominator separable digital filter is implemented in Altera Stratix III FPGA. The implementation achieves a data throughput equivalent to one multiplication and two additions, plus one clock cycle. It has been found that the maximum operating frequency of the implementation decreases with an increase in the order of the filter due to mainly the interconnect delay. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/CCECE.2011.6030528 | 2011 24TH CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (CCECE) |
Keywords | Field | DocType |
Digital filters, Digital signal processors, Field programmable gate arrays, Parallel processing | Stratix,Digital filter,Adder,Digital signal processor,Computer science,Field-programmable gate array,Electronic engineering,Multiplication,Throughput,Cycles per instruction | Conference |
ISSN | Citations | PageRank |
0840-7789 | 0 | 0.34 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Danny Teng-Hsiang Tsuei | 1 | 0 | 0.34 |
| Mohamed-Yahia Dabbagh | 2 | 0 | 0.34 |
| Manoj Sachdev | 3 | 669 | 88.45 |