Name
Abstract | ||
|---|---|---|
Negative Bias Temperature Instability (NBTI) is the leading factor of circuit performance degradation. Due to its complex dependence on operating conditions, especially signal probability, it is a tremendous challenge to accurately predict the degradation rate in reality. On the other hand, we demonstrate in this work that it is feasible to reliably predict the relative importance of gates under NBTI. By identifying critical gates that are the most important ones for timing degradation, we will be able to effectively protect the circuit from aging, with the minimum design overhead. The proposed method is based on a new timing analysis framework that integrates a NBTI-aware library. For each potential critical path, we prove that there exists a particular signal probability, which leads to the worst case of timing degradation. The search of such worst case signal probability provides a safe guardband for the degradation, yet avoiding overly pessimistic analysis. By applying this method to ISCAS and ITC benchmark circuits at the 65nm node, we demonstrate that in average only 1% of total gates need to be protected in order to control the timing degradation within 10% in ten years. Since this method only requires one-time analysis of each critical path, it is very efficient in computation. With the information of critical gates available, it further enables other resilient design techniques to mitigate circuit aging under NBTI. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ICCAD.2007.4397353 | ICCAD |
Keywords | Field | DocType |
new timing analysis framework,timing degradation,potential critical path,circuit performance degradation,critical gate,degradation rate,particular signal probability,one-time analysis,efficient method,critical path,itc benchmark circuit,high level synthesis,logic gates,timing analysis,operant conditioning,probability,negative bias temperature instability | Logic gate,Computer science,High-level synthesis,Electronic engineering,Degradation (geology),Real-time computing,Negative-bias temperature instability,Static timing analysis,Critical path method,Electronic circuit,Computation | Conference |
ISSN | ISBN | Citations |
1063-6757 | 1-4244-1382-6 | 97 |
PageRank | References | Authors |
5.04 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wenping Wang | 1 | 2491 | 176.19 |
| Zile Wei | 2 | 136 | 8.32 |
| Shengqi Yang | 3 | 482 | 27.52 |
| Yu Cao | 4 | 329 | 29.78 |