Yu Cao - Citegraph

Author Info

Name	Affiliation	Papers
YU CAO	Arizona State University, Tempe, AZ	28
Collaborators	Citations	PageRank
101	329	29.78
Referers	Referees	References
872	363	122

Search Limit

100872

Publications (28 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks	1	0.36	2022
System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration	0	0.34	2021
Robust Rram-Based In-Memory Computing In Light Of Model Stability	0	0.34	2021
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems	3	0.44	2020
Deep Neural Network Training Accelerator Designs in ASIC and FPGA	1	0.35	2020
Compact modeling and simulation of accelerated circuit aging	0	0.34	2018
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations.	2	0.36	2017
Duty cycle shift under static/dynamic aging in 28nm HK-MG technology	1	0.35	2015
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning	12	0.67	2015
On-chip Sparse Learning with Resistive Cross-point Array Architecture	3	0.40	2015
Exploring sub-20nm FinFET design with predictive technology models	84	6.54	2012
Design benchmarking to 7nm with FinFET predictive technology models	12	1.64	2012
Enhancing the Reliability of STT-RAM through Circuit and System Level Techniques	7	0.82	2012
Workload-adaptive process tuning strategy for power-efficient multi-core processors	2	0.41	2010
Workload-aware neuromorphic design of low-power supply voltage controller	4	0.40	2010
Compact Modeling of a PD SOI MESFET for Wide Temperature Designs	1	0.82	2009
Modeling of layout-dependent stress effect in CMOS design	8	1.07	2009
Design rule optimization of regular layout for leakage reduction in nanoscale design	7	1.03	2008
Reliable Systems on Unreliable Fabrics	23	1.10	2008
Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect	15	1.10	2008
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation	24	2.39	2007
Rigorous extraction of process variations for 65nm CMOS design	0	0.34	2007
An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology	12	0.89	2007
A New Simulation Method for NBTI Analysis in SPICE Environment	6	0.62	2007
An efficient method to identify critical gates under circuit aging	97	5.04	2007
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs	2	0.50	2006
Sram Cell Optimization For Ultra-Low Power Standby	2	0.79	2006
Statistical Leakage Minimization Of Digital Circuits Using Gate Sizing, Gate Length Biasing, And Threshold Voltage Selection	0	0.34	2006