Name
Abstract | ||
|---|---|---|
Almost all hardware platforms to date have been homogeneous with one or more identical processors managed by the operating system (OS). However, recently, it has been recognized that power constraints and the need for domain-specific high performance computing may lead architects towards building heterogeneous architectures and platforms in the near future. In this paper, we consider the three types of heterogeneous core architectures: (a) Virtual asymmetric cores: multiple processors that have identical core micro-architectures and ISA but each running at a different frequency point or perhaps having a different cache size, (b) Physically asymmetric cores: heterogeneous cores, each with a fundamentally different microarchitecture (in-order vs. out-of-order for instance) running at similar or different frequencies, with identical ISA and (c) Hybrid cores: multiple cores, where some cores have tightly-coupled hardware accelerators or special functional units. We show case studies that highlight why existing OS and hardware interaction in such heterogeneous architectures is inefficient and causes loss in application performance, throughput efficiency and lack of quality of service. We then discuss hardware and software support needed to address these challenges in heterogeneous platforms and establish efficient heterogeneous environments for platforms in the next decade. In particular, we will outline a monitoring and prediction framework for heterogeneity along with software support to take advantage of this information. Based on measurements on real platforms, we will show that these proposed techniques can provide significant advantage in terms of performance and power efficiency in heterogeneous platforms. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1945023.1945032 | Operating Systems Review |
Keywords | Field | DocType |
scheduling,different frequency,efficient heterogeneous environment,performance prediction,heterogeneous core,different microarchitecture,software support,heterogeneous platform,different cache size,heterogeneous core architecture,heterogeneous architecture,efficient interaction,different frequency point,special functions,operating system,quality of service,hardware accelerator,out of order,power efficiency | Supercomputer,Computer science,CPU cache,Scheduling (computing),Quality of service,Real-time computing,Software,Throughput,Multi-core processor,Distributed computing,Microarchitecture | Journal |
Volume | Issue | Citations |
45 | 1 | 31 |
PageRank | References | Authors |
1.23 | 13 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sadagopan Srinivasan | 1 | 120 | 7.87 |
| Li Zhao | 2 | 604 | 34.84 |
| Ramesh Illikkal | 3 | 481 | 33.98 |
| Ravishankar Iyer | 4 | 720 | 35.52 |