Name
Affiliation
Papers
RAVISHANKAR IYER
Intel Corporation, Santa Clara, CA 95052 USA
36
Collaborators
Citations 
PageRank 
90
720
35.52
Referers 
Referees 
References 
1751
1076
508
Search Limit
1001000
Title
Citations
PageRank
Year
The convergence of physical/digital worlds: implications on workloads & architecture00.342016
Domain knowledge based energy management in handhelds160.622015
Towards Distributed Video Summarization30.502015
Adaptive Keyframe Selection for Video Summarization90.532015
The future of fault tolerant computing00.342015
An evaluation of zookeeper for high availability in system S10.402014
Orchestrated scheduling and prefetching for GPGPUs871.892013
A Simulation Framework to Evaluate Virtual CPU Scheduling Algorithms20.362013
Machine Learning-Based Runtime Scheduler for Mobile Offloading Framework90.492013
OpenCL-Based Remote Offloading Framework for Trusted Mobile Cloud Computing00.342013
PCASA: probabilistic control-adjusted selective allocation for shared caches40.402012
SNARF: a social networking-inspired accelerator remoting framework50.442012
Exploiting semantics of virtual memory to improve the efficiency of the on-chip memory system00.342012
ISIS: An accelerator for Sphinx speech recognition30.412011
Cost-effectively offering private buffers in SoCs and CMPs20.362011
Keynote I: The era of heterogeneity: Are we prepared?00.342011
Hauberk: Lightweight Silent Data Corruption Error Detector for GPGPU502.122011
HeteroScouts: hardware assist for OS scheduling in heterogeneous CMPs30.452011
Shared Resource Monitoring and Throughput Optimization in Cloud-Computing Datacenters230.942011
Efficient interaction between OS and architecture in heterogeneous platforms311.232011
ACCESS: Smart scheduling for asymmetric cache CMPs170.672011
Quality of service shared cache management in chip multiprocessor architecture60.412010
CHOP: Adaptive filter-based DRAM caching for CMP server platforms702.472010
Performance characterization and acceleration of Optical Character Recognition on handheld platforms30.382010
Optimizing Communication And Capacity In A 3d Stacked Reconfigurable Cache Hierarchy411.772009
Architecture Support for Improving Bulk Memory Copying and Initialization Performance150.732009
Performance And Power Optimization Through Data Compression In Network-On-Chip Architectures441.742008
To Snoop or Not to Snoop: Evaluation of Fine-Grain and Coarse-Grain Snoop Filtering Techniques10.372008
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects271.322007
Constraint-aware large-scale CMP cache design30.412007
A Framework for Providing Quality of Service in Chip Multi-Processors662.442007
Processor-Level Selective Replication170.782007
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource1076.262006
Exploring the cache design space for large scale CMPs421.712005
Design and analysis of static memory management policies for CC-NUMA Multiprocessors80.752002
Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors50.482000