Name
Title | ||
|---|---|---|
A Two-Write And Two-Read Multi-Port Sram With Shared Write Bit-Line Scheme And Selective Read Path For Low Power Operation |
Abstract | ||
|---|---|---|
This paper proposes a two-write and two-read (2W2R) bit-cell for a multi-port (MP) SRAM design to improve the static noise margin (SNM) and solve the write-disturb issues of nanoscale CMOS technologies. Using an additional Y-access MOS (column-direction access transistor), the 2W2R MP SRAM adopts a scheme of combining the row access transistor and sharing write bit-line with an adjacent bit cell. This scheme halves the write bit-line number and mitigates the write current consumption caused by pre-charging the bit-line to V-DD. This paper also proposes a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual V-SS controlled by a Y-select signal reduces read-port current consumption. Results show that the proposed design reduces both the write current and read current consumption by 30%, compared to the conventional MP structure, from 1.3 V to 0.6 V V-DD. The proposed 8 Kb 2W2R MP SRAM was fabricated on the test chip using TSMC 40 nm CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1166/jolpe.2013.1236 | JOURNAL OF LOW POWER ELECTRONICS |
Keywords | Field | DocType |
Multi-Port, SRAM, Write-Disturb, Half-Select, Read Path | Multi port,Computer science,Static random-access memory,Chip,CMOS,Electronic engineering,Ground,Computer hardware,Transistor,Bit cell,Write bit | Journal |
Volume | Issue | ISSN |
9 | 1 | 1546-1998 |
Citations | PageRank | References |
3 | 0.57 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dao-Ping Wang | 1 | 5 | 1.32 |
| Hon-Jarn Lin | 2 | 8 | 2.07 |
| Wei Hwang | 3 | 254 | 44.40 |