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HON-JARN LIN
Author Info
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Name
Affiliation
Papers
HON-JARN LIN
Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
5
Collaborators
Citations
PageRank
19
8
2.07
Referers
Referees
References
41
48
12
Publications (5 rows)
Collaborators (19 rows)
Referers (41 rows)
Referees (48 rows)
Title
Citations
PageRank
Year
13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference.
0
0.34
2020
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math></inline-formula> A Sensing Resolution, and 17.5-nS Read Access Time
2
0.41
2019
A 1.4Mb 40-nm embedded ReRAM macro with 0.07um<sup>2</sup> bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application
1
0.35
2017
Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
2
0.40
2014
A Two-Write And Two-Read Multi-Port Sram With Shared Write Bit-Line Scheme And Selective Read Path For Low Power Operation
3
0.57
2013
1