Name
Abstract | ||
|---|---|---|
Recently, most 3D graphics rendering processors include a pixel cache storing z-data and color data to reduce the memory latency and bandwidth requirement. In this paper, we propose an effective pixel cache architecture to improve the performance of the rendering processors. z-Data are selectively stored into either a main cache or an auxiliary buffer based on the result of z-test, while color data are stored into the auxiliary buffer. Simulation results show that the 16KB proposed cache architecture provides better performance than the 32KB conventional cache architecture. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1016/j.micpro.2004.05.004 | Microprocessors and Microsystems |
Keywords | Field | DocType |
Rendering processor,Pixel cache,Z-test | Cache invalidation,Cache pollution,Computer science,Snoopy cache,Cache,Parallel computing,Page cache,Real-time computing,Cache algorithms,Cache coloring,Computer hardware,Smart Cache | Journal |
Volume | Issue | ISSN |
29 | 1 | 0141-9331 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kil-Whan Lee | 1 | 18 | 3.29 |
| Woo-Chan Park | 2 | 108 | 19.82 |
| Il-San Kim | 3 | 14 | 2.82 |
| Tack-Don Han | 4 | 351 | 66.39 |