Name
Abstract | ||
|---|---|---|
Chip performance and density fire increasing tremendously and the CAD tools are are always lagging behind In this paper we introduce a functional timing verifier using a novel fuzzy delay model which bridges the gap between the front-end timing verification and the back-end delay fault testing. The proposed fuzzy delay model can handle uncertainties with respect to timing characteristics, and manufacturing anomalies. Experimental results are presented for the ISCAS-85 bench,nark circuits. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ICVD.1999.745153 | VLSI Design |
Keywords | Field | DocType |
novel fuzzy delay model,functional timing verifier,fuzzy set theory,uncertainty,integrated circuit design,front end,fabrication,chip | Delay calculation,Computer science,Fuzzy logic,Real-time computing,Electronic engineering,Fuzzy set,Control engineering,Chip,Integrated circuit design,Static timing analysis,Electronic circuit,Lagging | Conference |
ISBN | Citations | PageRank |
0-7695-0013-7 | 0 | 0.34 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. Jayabharathi | 1 | 12 | 4.42 |
| M. d'Abreu | 2 | 28 | 11.29 |
| J. Abraham | 3 | 4905 | 608.16 |