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R. JAYABHARATHI
Author Info
Open Visualization
Name
Affiliation
Papers
R. JAYABHARATHI
Intel Corp, Log Test Technol, Folsom, CA USA
12
Collaborators
Citations
PageRank
18
12
4.42
Referers
Referees
References
33
166
110
Search Limit
100
166
Publications (12 rows)
Collaborators (18 rows)
Referers (33 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection.
0
0.34
2016
Non-enumerative correlation-aware path selection
1
0.35
2015
Hybrid 3D pre-bonding test framework design
1
0.36
2013
Non-enumerative generation of statistical path delays for ATPG
0
0.34
2012
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model
3
0.39
2006
Exact At-Speed Delay Fault Grading In Sequential Circuits
0
0.34
2006
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
2
0.37
2005
SpeedGrade: An RTL Path Delay Fault Simulator
3
0.41
2001
DPDAT: data path direct access testing
1
0.49
2001
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model
0
0.34
1999
A Novel Solution for Chip-Level Functional Timing Verification
1
0.37
1997
A Comparative Evaluation of Adders Based on Performance and Testability
0
0.34
1993
1