Name
Title | ||
|---|---|---|
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset |
Abstract | ||
|---|---|---|
The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple node upset, i.e. a transient or soft fault affecting any two nodes in a cell. The proposed hardened memory cell utilizes a Schmitt trigger design; simulation shows that the multiple node upset tolerance is improved by nearly twice as much over existing designs. Moreover the 13T cell achieves a 33% reduction in write delay and only a 5% increase in power consumption compared to the DICE cell (consisting of 12 transistors). Simulation results are provided using the predictive technology file for 32nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple node upset tolerance of the proposed memory cell in the presence of process, voltage, and temperature variations in their designs. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ICCD.2011.6081418 | ICCD |
Keywords | Field | DocType |
process variation,multiple node upset,power supply voltage scaling,dice cell,single event,write delay,power consumption,memory cell,nanoscale memory cell design,memory design,integrated circuit modelling,13t memory cell configuration,monte carlo simulation,multiple node,nanoscale memory cell modeling,memory cell configuration,multiple-node upset tolerance,nanoscale cmos,memory cell hardening,nanoscale memory cell,trigger circuits,feature size,nanotechnology,comprehensive treatment,proposed memory cell,likely multiple node upset,size 32 nm,monte carlo methods,integrated circuit design,proposed hardened memory cell,schmitt trigger design,radiation hardening,multiple node upset tolerance,voltage variation,temperature variation,predictive technology file,soft error,nanoelectronics,device size reduction,radiation hardening (electronics),cmos memory circuits,cmos integrated circuits,feedback loop,memory management,transistors | Nanoelectronics,Soft error,Schmitt trigger,Computer science,Real-time computing,Electronic engineering,CMOS,Integrated circuit design,Memory management,Upset,Memory cell | Conference |
ISSN | ISBN | Citations |
1063-6404 | 978-1-4577-1953-0 | 1 |
PageRank | References | Authors |
0.36 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sheng Lin | 1 | 139 | 14.39 |
| Yong-bin Kim | 2 | 338 | 55.72 |
| Fabrizio Lombardi | 3 | 1985 | 259.25 |