Yong-bin Kim - Citegraph

Author Info

Name	Affiliation	Papers
YONG-BIN KIM	Northeastern Univ, Dept Elect & Comp Engn, Marine Sci Ctr, Boston, MA 02115 USA	104
Collaborators	Citations	PageRank
104	338	55.72
Referers	Referees	References
842	1056	486

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Publications (100 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Tunable High-Gain Low-Noise Transimpedance Amplifier for Biosensing.	0	0.34	2020
Area Efficient Multi-Threshold Null Convenction Logic	0	0.34	2019
10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance	0	0.34	2019
Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor	0	0.34	2018
A Quarter-Rate 3-Tap Dfe For 4gbps Data Rate With Switched-Capapctiors Based 1st Speculative Tap	0	0.34	2017
Integrated circuits design using carbon nanotube field effect transistor	0	0.34	2016
A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration	0	0.34	2016
A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC.	1	0.36	2016
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories	1	0.36	2016
An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction	1	0.40	2016
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier	0	0.34	2015
A process tolerant semi-self impedance calibration method for LPDDR4 memory controller	1	0.44	2015
A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer	2	0.44	2015
Asynchronous advanced encryption standard hardware with random noise injection for improved side-channel attack resistance	7	0.53	2014
A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters	1	0.43	2014
A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers	0	0.34	2014
A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers	2	0.40	2014
A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch	3	0.44	2014
An area efficient low power high speed S-Box implementation using power-gated PLA	0	0.34	2014
A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA	0	0.34	2014
A novel self-calibration scheme for 12-bit 50MS/s SAR ADC	0	0.34	2014
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches	2	0.43	2014
A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method	0	0.34	2013
A high performance modulo 2 n +1 squarer design based on carbon nanotube technology	0	0.34	2013
A 10-bit 64MS/s SAR ADC using variable clock period method	0	0.34	2013
A fully integrated switched-capacitor DC-DC converter with dual output for low power application	2	0.46	2012
Soft error masking latch for sub-threshold voltage operation	1	0.37	2012
A novel sort error hardened 10T SRAM cells for low voltage operation	8	0.83	2012
A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss	1	0.36	2012
On-chip HBD sensor for nanoscale CMOS technology	1	0.36	2012
A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter.	3	0.65	2012
Low power, high PVT variation tolerant central pattern generator design for a bio-hybrid micro robot	3	0.44	2012
A design and integration of Parametric Measurement Unit on to a 600MHz DCL	0	0.34	2012
A high speed low power modulo 2n+1 multiplier design using carbon-nanotube technology	0	0.34	2012
Post-configuration repair strategy for asynchronous nanowire crossbar system	0	0.34	2012
Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system	0	0.34	2012
A low stand-by power start-up circuit for SMPS PWM controller	0	0.34	2012
All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter	0	0.34	2012
Design and evaluation of Side Channel Attack resistant asynchronous AES Round Function	0	0.34	2012
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS	18	1.25	2011
A 11-transistor nanoscale CMOS memory cell for hardening to soft errors	21	1.07	2011
A design approach of a Parametric Measurement Unit on to a 600MHz DCL	0	0.34	2011
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset	1	0.36	2011
Modelling a CNTFET with Undeposited CNT Defects	1	0.44	2010
A low-offset high-speed double-tail dual-rail dynamic latched comparator	0	0.34	2010
High speed and low power transceiver design with CNFET and CNT bundle interconnect.	7	0.80	2010
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems	13	1.03	2010
8Gb/s capacitive low power and high speed 4-PWAM transceiver design	0	0.34	2010
A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier	0	0.34	2010
Performance assessment of analog circuits with carbon nanotube FET (CNFET)	1	0.38	2010

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