Name
Abstract | ||
|---|---|---|
In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1007/s10836-010-5187-2 | J. Electronic Testing |
Keywords | Field | DocType |
Built-in self-test (BIST),Digital-to-analog converters (DACs),Non-linearity errors,Selected-code method | Integral nonlinearity,Oscillation,Computer science,Linearity,Electronic engineering,Real-time computing,Converters,Sampling (statistics),Built-in self-test | Journal |
Volume | Issue | ISSN |
27 | 1 | 0923-8174 |
Citations | PageRank | References |
4 | 0.70 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsin-Wen Ting | 1 | 41 | 8.81 |
| Soon-Jyh Chang | 2 | 655 | 73.67 |
| Su-Ling Huang | 3 | 4 | 0.70 |