Name
Abstract | ||
|---|---|---|
Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these modules, multipliers consume the largest amount of power due to their size and complexity. We propose low power BIST schemes for datapath architectures built around multiplier-accumulator pairs, based on deterministic test patterns. Two alternatives are proposed depending on whether the target is low energy dissipation during a BIST session or low power dissipation (i.e. average energy dissipation between successive test vectors). The proposed BIST schemes are more efficient than pseudorandom BIST for the same high fault coverage target. Up to 78.33% energy, saving is achieved by the proposed low energy BIST scheme and up to 82.22% power, saving is achieved by the proposed low power BIST scheme, compared with pseudorandom BIST. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/VTEST.2000.843822 | VTS |
Keywords | Field | DocType |
automatic test pattern generation,built-in self test,digital signal processing chips,microprocessor chips,multiplying circuits,DSPs,datapaths,deterministic test patterns,functional modules,low energy BIST scheme,low power BIST scheme,microprocessors,multiplier-accumulator pairs,processing cores,successive test vectors | Automatic test pattern generation,Power saving,Datapath,Fault coverage,Low energy,Computer science,Dissipation,Real-time computing,Electronic engineering,Built-in self-test,Pseudorandom number generator | Conference |
ISBN | Citations | PageRank |
0-7695-0613-5 | 18 | 1.26 |
References | Authors | |
14 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Gizopoulos | 1 | 269 | 21.51 |
| N. Kranitis | 2 | 138 | 11.15 |
| M. Psarakis | 3 | 92 | 8.13 |
| A. Paschalis | 4 | 358 | 31.08 |
| Y. Zorian | 5 | 499 | 47.97 |