| Extending fault periodicity table for testing faults in memories under 20nm | 2 | 0.43 | 2014 |
| An effective solution for building memory BIST infrastructure based on fault periodicity | 0 | 0.34 | 2013 |
| Generic BIST architecture for testing of content addressable memories | 6 | 0.64 | 2011 |
| An efficient March test for detection of all two-operation dynamic faults from subclass Sav | 0 | 0.34 | 2010 |
| Test and reliability concerns for 3D-ICs | 1 | 0.37 | 2010 |
| Minimal March Tests for Detection of Dynamic Faults in Random Access Memories | 0 | 0.34 | 2007 |
| Minimal March-Based Fault Location Algorithm with Partial Diagnosis for All Static Faults in Random Access Memories | 4 | 0.44 | 2006 |
| Minimal March Tests for Dynamic Faults in Random Access Memories | 5 | 0.45 | 2006 |
| Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories | 10 | 0.82 | 2006 |
| Minimal March Tests for Unlinked Static Faults in Random Access Memories | 14 | 0.89 | 2005 |
| Impact of Soft Error Challenge on SoC Design | 4 | 0.56 | 2005 |
| Guest Editors' Introduction: Design for Yield and Reliability | 24 | 2.11 | 2004 |
| Fault Isolation Using Tests for Non-Isolated Blocks | 0 | 0.34 | 2002 |
| Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA | 0 | 0.34 | 2002 |
| Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers | 3 | 0.41 | 2001 |
| IS-FPGA: A New Symmetric FPGA Architecture with Implicit SCAN | 23 | 1.53 | 2001 |
| Embedded tutorial: TRP: integrating embedded test and ATE | 0 | 0.34 | 2001 |
| A Discussion on Test Pattern Generation for FPGA—Implemented Circuits | 1 | 0.37 | 2001 |
| Different experiments in test generation for XILINX FPGAs | 22 | 1.43 | 2000 |
| Testing the Local Interconnect Resources of SRAM-Based FPGA's | 6 | 0.56 | 2000 |
| Low Power/Energy BIST Scheme for Datapaths | 18 | 1.26 | 2000 |
| An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family | 2 | 0.43 | 2000 |
| Minimizing the Number of Test Configurations for Different FPGA Families | 13 | 0.95 | 1999 |
| Scaling deeper to submicron: on-line testing to the rescue | 7 | 0.90 | 1999 |
| SRAM-Based FPGAs: Testing the Embedded RAM Modules | 15 | 1.08 | 1999 |
| Testing the configurable interconnect/logic interface of SRAM-based FPGA's | 10 | 0.76 | 1999 |
| Challenges in testing core-based system ICs | 31 | 4.86 | 1999 |
| Test Configuration Minimization for the Logic Cells of SRAM-Based FPGAs: A Case Study | 5 | 0.52 | 1999 |
| SRAM-based FPGA's: testing the interconnect/logic interface | 4 | 0.50 | 1998 |
| Built-in-self-test with an alternating output | 1 | 0.41 | 1998 |
| On-Line Testing for VLSI—A Compendium of Approaches | 118 | 9.42 | 1998 |
| RAM-based FPGA's: a test approach for the configurable logic | 18 | 1.30 | 1998 |
| Test of RAM-based FPGA: methodology and application to the interconnect | 71 | 6.18 | 1997 |
| Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA | 19 | 1.09 | 1997 |
| An effective BIST scheme for carry-save and carry-propagate array multipliers | 15 | 1.11 | 1995 |
| Optimizing error masking in BIST by output data modification | 20 | 2.78 | 1990 |
| Higher certainty of error coverage by output data modification | 7 | 1.37 | 1984 |
