Name
Abstract | ||
|---|---|---|
As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power-mode-aware clock tree often suffers from a huge overhead on power consumption. Moreover, at the ULV level, since the setup time and the hold time of each register dramatically increase, the number of timing violations also increases greatly. However, the existing minimum padding technique cannot fix hold time violations in multiple power modes. Based on those two observations, in this paper, we propose a low-power timing closure methodology, which incorporates the synthesis of clock tree and data path, for multi-power-mode ULV designs. Our low-power timing closure methodology has two main approaches. First, we use multiple power modes to build a power-mode-aware clock tree for reducing clock skew with very small power consumption. Second, we propose the first multi-power-mode minimum padding technique to fix all the hold time violations in all the power modes simultaneously. Experimental results consistently show that the integration of both approaches yields the best results.
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Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCAD.2013.6691191 | ICCAD |
Keywords | Field | DocType |
power consumption,multiple power mode,clock tree,conventional power-mode-aware clock tree,ultra-low voltage design,wide voltage range,minimum padding technique,low-power electronics,power mode,multiple power modes,power-mode-aware clock tree,different power mode,clocks,small power consumption,low-power timing closure methodology,supply voltage,ultra-low voltage designs,clock skew,huge clock skew,biochip,sample preparation,low power electronics,dilution | Timing failure,Clock gating,Computer science,Real-time computing,Electronic engineering,Clock skew,Low voltage,Digital clock manager,Padding,Timing closure,Low-power electronics | Conference |
ISSN | ISBN | Citations |
1092-3152 | 978-1-4799-1069-4 | 6 |
PageRank | References | Authors |
0.57 | 10 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-Pin Tu | 1 | 21 | 4.32 |
| Chung-Han Chou | 2 | 39 | 3.73 |
| Shih-Hsu Huang | 3 | 203 | 38.89 |
| Shih-Chieh Chang | 4 | 641 | 52.31 |
| Yow-Tyng Nieh | 5 | 108 | 9.61 |
| Chien-Yung Chou | 6 | 8 | 0.99 |