Paper Info
Title
Design of Sequential Elements for Low Power Clocking System
Abstract
Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.
Year
DOI
Venue
2011
10.1109/TVLSI.2009.2038705
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
sequential circuits,power consumption,clock distribution network,low power clocking system,clocking system,sequential element,clocked transistor,low-power electronics,sequential elements,clock system,clocked pair shared flip-flop,integrated circuit design,low power,local clocked transistor,flip-flops,clock load,flip-flop,clock and data recovery circuits,double edge clocking,chip power,master slave,low power electronics,packaging,system on a chip,chip,network on a chip,system performance
Sequential logic,System on a chip,Computer science,Clock domain crossing,Network on a chip,Real-time computing,Electronic engineering,Integrated circuit design,Flip-flop,Energy consumption,Low-power electronics
Journal
Volume
Issue
ISSN
19
5
1063-8210
Citations 
PageRank 
References 
10
0.79
14
Authors
5
Name
Order
Citations
PageRank
Peiyi Zhao1969.81
Jason McNeely2373.97
Weidong Kuang3706.95
Nan Wang4111.27
Zhongfeng Wang521654.57