Name
Abstract | ||
|---|---|---|
In this work, we present a new error control method to improve the energy efficiency and reliability of network-on-chip (NoC) links. The proposed method combines the error control coding (ECC) capabilities of the NoC's datalink and network layers to dynamically adjust the error control strength in variable noise conditions. Network-layer ECC is used in low noise conditions and error control strength is enhanced by adding datalink-layer ECC in high noise regions. To switch between the two ECC modes at runtime without interrupting normal operation, we propose a dual-layer cooperative error control protocol and its hardware-efficient implementation using the concept of product codes. Theoretical analyses of residual error rate and performance show the proposed method outperforms previous single-layer fixed and adaptive error control schemes. Compared to previous solutions, the proposed method reduces residual packet error rate by up to four orders of magnitude, achieves up to 72% energy reduction and improves average latency by up to 64%. The energy and latency reduction benefits are maintained as the routing path length and packet size increase, at the cost of a moderate increase in area overhead. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TVLSI.2011.2156436 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
error correction codes,integrated circuit interconnections,integrated circuit reliability,network routing,network-on-chip,area overhead,datalink layer,dual layer adaptive error control,dual layer cooperative error control protocol,energy efficiency,energy reduction,error control coding,latency reduction,network layer,network-on-chip links,product codes,reliability,residual packet error rate,routing path length,Energy efficiency,error control coding (ECC),network-on-chip (NoC),on-chip interconnect,product code,reliability,transient error | Residual,Universal Product Code,Computer science,Efficient energy use,Network packet,Network on a chip,Electronic engineering,Real-time computing,Error detection and correction,Codec,Bit error rate | Journal |
Volume | Issue | ISSN |
20 | 7 | 1063-8210 |
Citations | PageRank | References |
11 | 0.57 | 19 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Qiaoyan Yu | 1 | 174 | 28.58 |
| Paul Ampadu | 2 | 285 | 28.55 |