Name
Abstract | ||
|---|---|---|
This paper deals with testing of inter-port faults in multi-port Static Random Access Memories (SRAMs). A inter-port fault is caused by a short between word/bit lines of different ports in a multi-port SRAM. By considering different implementations of the SRAM and its layout, an approach, which achieves 100 % coverage of fault detection, is proposed.This two-step approach is based on two novel algorithms, MMCA (Modified March C Algorithm) and WIPD (Write Inter-Port Detection). It is shown that inter-port fault detection is a combinatorial problem; hence, MMCA and WIPD must be executed multiple times depending on the types, number of ports and line arrangement in the layout. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/VTEST.2000.843858 | VTS |
Keywords | Field | DocType |
SRAM chips,automatic testing,fault diagnosis,integrated circuit testing,multiport networks,MMCA,WIPD,combinatorial problem,fault detection,inter-port faults,line arrangement,modified March C algorithm,multi-port static RAMs,two-step approach,word/bit lines,write inter-port detection | Port (computer networking),Bit line,Fault detection and isolation,Computer science,Multi port,Read-write memory,Parallel computing,Automatic testing,Electronic engineering,Static random-access memory,Real-time computing,Random access | Conference |
ISBN | Citations | PageRank |
0-7695-0613-5 | 20 | 1.32 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Zhao | 1 | 215 | 13.07 |
| S. Irrinki | 2 | 24 | 2.21 |
| M. Puri | 3 | 20 | 1.32 |
| F. Lombardi | 4 | 122 | 15.25 |