Paper Info
Title
A Reduced-Sample-Rate Sigma-Delta-Pipeline Adc Architecture For High-Speed High-Resolution Applications
Abstract
A reduced-sample-rate (RSR) sigma-delta-pipeline (SDP) analog-to-digital converter architecture suitable for high-resolution and high-speed applications with low oversampling ratios (OSR) is presented. The proposed architecture employs a class of high-order noise transfer function (NTF) with a novel pole-zero locations. A design methodology is developed to reach the optimum NTF The optimum NTF determines the location of the non-zero poles improving the stability of the loop and implementing the reduced-sample-rate structure, simultaneously. Unity gain signal transfer function to mitigate the analog circuit imperfections, simplified analog implementation with reduced number of operational transconductance amplifiers (OTAs), and novel, aggressive yet stable NTF with high out of band gain to achieve larger peak signal-to-noise ratio (SNR) are the main features of the proposed NTF and ADC architecture. To verify the usefulness of the proposed architecture, NTF, and design methodology, two different cases are investigated. Simulation results show that with a 4th-order modulator, designed making use of the proposed approach, the maximum SNDR of 115 dB and 124.1 dB can be achieved with only OSR of 8, and 16 respectively.
Year
DOI
Venue
2006
10.1093/ietele/e89-c.6.692
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
sigma-delta-pipeline, reduced-sample-rate architecture, switched-capacitor circuit, IIR filters, single OTA implementation
Oversampling,Infinite impulse response,Sampling (signal processing),Signal-to-noise ratio,Delta-sigma modulation,Electronic engineering,Transfer function,Engineering,Signal transfer function,Operational amplifier
Journal
Volume
Issue
ISSN
E89C
6
1745-1353
Citations 
PageRank 
References 
0
0.34
0
Authors
2
Name
Order
Citations
PageRank
Vahid Majidzadeh161.57
Omid Shoaei213440.66