| A 7.2µW Magnitude/Phase Bio-impedance Measurement Front-End with PWM Output in 0.18µm CMOS | 0 | 0.34 | 2021 |
| An Asynchronous Pulse Width Modulator For Dc-Dc Buck Converter | 0 | 0.34 | 2020 |
| A Comprehensive Circuit Model For Evaluating The Response Of Silicon Photomultipliers In Continuous Wave Light Regime | 0 | 0.34 | 2019 |
| A Fully Fail-Safe Capacitive-Based Charge Metering Method for Active Charge Balancing in Deep Brain Stimulation | 0 | 0.34 | 2018 |
| A 0.5 μA/Channel front-end for implantable and external ambulatory ECG recorders. | 0 | 0.34 | 2018 |
| Statistical estimation of delay in nano-scale CMOS circuits using Burr Distribution. | 1 | 0.36 | 2018 |
| Enhanced Power-Delivered-to-Load Through Planar Multiple-Harmonic Wireless Power Transmission. | 1 | 0.41 | 2018 |
| Mixed-Signal IC With Pulse Width Modulation Wireless Telemetry for Implantable Cardiac Pacemakers in 0.18-μm CMOS. | 1 | 0.41 | 2018 |
| Distributed-Element Modelling For Spiral Resonators Used In Wireless Power Transfer | 1 | 0.40 | 2018 |
| A 1.55 μW Bio-Impedance Measurement System for Implantable Cardiac Pacemakers in 0.18 μm CMOS. | 3 | 0.51 | 2018 |
| Knock signal denoising employing a new time domain method | 0 | 0.34 | 2017 |
| A Power optimized switched-capacitor based approach in voltage-controlled cardiac stimulation | 0 | 0.34 | 2016 |
| A charge-pump based multi-mode stimuli generator for cardiac pacemaking | 0 | 0.34 | 2016 |
| Extended coupling-range wireless power transfer using 0× / 4× resonant regulating rectifier | 0 | 0.34 | 2016 |
| A wireless pulsed-current battery charger for implantable biomedical stimulators | 0 | 0.34 | 2016 |
| A simple and precise charge balancing method for voltage mode stimulation | 2 | 0.49 | 2014 |
| High speed sample and hold design using closed-loop pole-zero cancelation | 0 | 0.34 | 2011 |
| A High IIP2 Mixer Enhanced by a New Calibration Technique for Zero-IF Receivers | 14 | 1.09 | 2008 |
| An IIP2 Calibration Technique for Zero-IF Multi Band down Converter Mixer | 0 | 0.34 | 2008 |
| A Low-Voltage Low-Power Highly-Linear Switched-Rc Mdac For Pipelined Adcs | 1 | 0.43 | 2008 |
| A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS | 1 | 0.43 | 2008 |
| New technique in design of active rf cmos mixers for low flicker noise and high conversion gain | 0 | 0.34 | 2008 |
| A New Inductor-Less Ip2 Enhancement Technique For Cmos Multi-Standard Mixer | 0 | 0.34 | 2007 |
| A New IIP2 Enhancement Technique for CMOS Down-Converter Mixers | 6 | 0.60 | 2007 |
| A Reduced-Sample-Rate Sigma-Delta-Pipeline Adc Architecture For High-Speed High-Resolution Applications | 0 | 0.34 | 2006 |
| A New Approach For Dac Non-Linearity Compensation In Continuous Time Delta Sigma Modulators | 0 | 0.34 | 2006 |
| A New Infrastructure For Digital Pre-Filtering In Multi-Bit Continuous Time Delta Sigma Modulators | 1 | 0.43 | 2006 |
| A power optimized design methodology for low-distortion sigma-delta-pipeline ADCs | 2 | 0.40 | 2006 |
| A new structure for capacitor-mismatch-insensitive multiply-by-two amplification | 4 | 0.67 | 2006 |
| A low power, transverse analog FIR filter for feed forward equalization of gigabit Ethernet | 0 | 0.34 | 2006 |
| Double-Sampling Single-Loop Sigma-Delta Modulator Topologies for Broadband Applications | 0 | 0.34 | 2006 |
| Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios | 0 | 0.34 | 2006 |
| Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation | 2 | 0.43 | 2006 |
| A Novel Structure For The Design Of 2-1-1 Cascaded Continuous Time Delta Sigma Modulators | 2 | 0.61 | 2006 |
| Analysis of the Clock Jitter Effects in a Time Invariant Model of Continuous Time Delta Sigma Modulators | 1 | 0.48 | 2006 |
| Double-sampling single-loop ΣΔ modulator topologies for broad-band applications. | 0 | 0.34 | 2006 |
| Continuous Time Delta-Sigma Modulators with Arbitrary DAC Waveforms | 0 | 0.34 | 2006 |
| Power consumption issues in high-speed high-resolution pipelined A/D converters | 0 | 0.34 | 2005 |
| Modeling of switched-capacitor delta-sigma Modulators in SIMULINK | 28 | 2.87 | 2005 |
| A two-stage genetic algorithm method for optimization the Sigma-Delta modulators | 0 | 0.34 | 2005 |
| Power spectral density estimation of the clock jitter in a continuous time Delta Sigma modulator with non return to-zero DAC waveform | 0 | 0.34 | 2005 |
| Efficient Double-Sampled Cascaded Sigma Delta Modulator Topologies For Low Osrs | 0 | 0.34 | 2005 |
| A New Method for Elimination of the Clock Jitter Effects in Continuous Time Delta-Sigma Modulators | 0 | 0.34 | 2005 |
| A novel fully-differential class AB folded-cascode OTA for switched-capacitor applications. | 1 | 0.41 | 2005 |
| A 2/5 Mw Cmos Delta Sigma Modulator Employed In An Improved Gsm/Umts Receiver Structure | 0 | 0.34 | 2005 |
| A Simplified Illustration of Arbitrary DAC Waveform Effects in Continuous Time Delta-Sigma Modulators | 2 | 0.60 | 2005 |
| A dynamic start-up circuit for low voltage CMOS current mirrors with power-down support | 2 | 0.56 | 2005 |
| A Complete Analysis Of Noise In Inductively Source Degenerated Cmos Lna'S | 2 | 0.55 | 2005 |
| An accurate analysis of slew rate for two-stage CMOS opamps. | 5 | 0.88 | 2005 |
| Systematic design for optimization of high-resolution pipelined ADCs | 1 | 0.39 | 2004 |
