Name
Title | ||
|---|---|---|
Pvt: Unified Reduction Of Test Power, Volume, And Test Time Using Double-Tree Scan Architecture |
Abstract | ||
|---|---|---|
The double-tree scan (DTS) architecture was originally proposed for reducing power consumption in test mode. In this paper, we show that DTS supports variability of loading the same test vector to the scan path dynamically. This feature enhances linear independence of broadcast based compression, which in consequence, reduces the test application time and test data volume under external testing. Unlike the linear scan chain, there are multiple paths from the source to the sink in the DTS. Thus, each pattern can be loaded into scan chains in different ways, to break the correlation in traditional broadcast loading mode. Combining the flexibility of DTS with the broadcast-scan architecture to load different DTS-based scan chains simultaneously, we reduce test data and test application time. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1166/jolpe.2010.1088 | JOURNAL OF LOW POWER ELECTRONICS |
Keywords | Field | DocType |
External Testing, Test Power Minimization, Test Time Reduction, Test Data Reduction, Nonlinear Scan-Path Architecture | Design for testing,Test vector,Automatic test pattern generation,Linear independence,Electronic engineering,Real-time computing,Test data,Engineering,Test compression,Low-power electronics,Whippletree | Journal |
Volume | Issue | ISSN |
6 | 3 | 1546-1998 |
Citations | PageRank | References |
1 | 0.37 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhen Chen | 1 | 218 | 36.23 |
| Sharad C. Seth | 2 | 671 | 93.61 |
| Dong Xiang | 3 | 528 | 48.34 |
| Bhargab B. Bhattacharya | 4 | 848 | 118.02 |