Leverage Redundancy In Hardware Transactional Memory To Improve Cache Reliability | 0 | 0.34 | 2018 |
Exploiting FIFO Scheduler to Improve Parallel Garbage Collection Performance. | 1 | 0.35 | 2016 |
Converting heterogeneous statistical tables on the web to searchable databases. | 4 | 0.43 | 2016 |
SmartStealing: Analysis and Optimization of Work Stealing in Parallel Garbage Collection for Java VM | 2 | 0.37 | 2015 |
Factors affecting scalability of multithreaded Java applications on manycore systems | 2 | 0.37 | 2015 |
Transforming Web Tables to a Relational Database | 4 | 0.42 | 2014 |
End-to-End Conversion of HTML Tables for Populating a Relational Database | 0 | 0.34 | 2014 |
CLU: Co-Optimizing Locality and Utility in Thread-Aware Capacity Management for Shared Last Level Caches | 8 | 0.50 | 2014 |
Locality & utility co-optimization for practical capacity management of shared last level caches | 5 | 0.43 | 2012 |
Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching | 5 | 0.49 | 2010 |
Pvt: Unified Reduction Of Test Power, Volume, And Test Time Using Double-Tree Scan Architecture | 1 | 0.37 | 2010 |
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches | 18 | 0.69 | 2010 |
A novel hybrid delay testing scheme with low test power, volume, and time | 1 | 0.35 | 2010 |
Education | 0 | 0.34 | 2009 |
Comment: projection methods require black border removal. | 2 | 0.39 | 2009 |
Efficient Selection of Observation Points for Functional Tests | 2 | 0.38 | 2008 |
Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid | 2 | 0.37 | 2008 |
Efficient RTL Coverage Metric for Functional Test Selection | 8 | 0.53 | 2007 |
Efficient Test Compaction for Pseudo-Random Testing | 7 | 0.47 | 2005 |
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design | 6 | 0.47 | 2005 |
A Feature-Based Approach To Conflation Of Geospatial Sources | 52 | 2.28 | 2004 |
Low-Energy BIST Design for Scan-based Logic Circuits | 8 | 0.56 | 2003 |
Modeling Fault Coverage of Random Test Patterns | 9 | 0.59 | 2003 |
A Novel Method to Improve the Test Efficiency of VLSI Tests | 0 | 0.34 | 2002 |
Design Verification And Functional Testing Of Finite State Machines | 0 | 0.34 | 2001 |
Adaptive Segmentation of Document Images | 4 | 0.52 | 2001 |
Integrated text and line-art extraction from a topographic map | 22 | 1.07 | 2000 |
Empirical computation of reject ratio in VLSI testing | 1 | 0.34 | 1999 |
Synthesis for Testability by Two-Clock Control | 3 | 0.42 | 1997 |
A Prototype for Adaptive Association of Street Names with Streets on Maps | 2 | 0.35 | 1997 |
Improving Circuit Testability by Clock Control | 8 | 0.64 | 1996 |
HGA: a hardware-based genetic algorithm | 72 | 8.12 | 1995 |
A system for recognizing a large class of engineering drawings | 36 | 1.64 | 1995 |
A switch-level test generation system for synchronous and asynchronous circuits | 4 | 0.40 | 1995 |
Syntactic segmentation and labeling of digitized pages from technical journals | 75 | 5.52 | 1993 |
Clock partitioning for testability | 12 | 0.78 | 1993 |
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits | 5 | 0.91 | 1992 |
A Switch-Level Test Generation System. | 2 | 0.39 | 1992 |
A prototype document image analysis system for technical journals | 188 | 31.54 | 1992 |
Estimating the Quality of Manufactured Digital Sequential Circuits | 6 | 0.89 | 1991 |
An Experimental Study on Reject Ratio Prediction for VLSI Circuits: Kokomo Revisited | 35 | 8.37 | 1990 |
Testability analysis of synchronous sequential circuits based on structural data | 10 | 10.33 | 1989 |
A new model for computation of probabilistic testability in combinational circuits | 26 | 4.25 | 1989 |
A fast fault simulation algorithm for combinational circuits | 10 | 3.46 | 1988 |
Predicting Fault Coverage from Probabilistic Testability | 2 | 0.48 | 1985 |
LSI product quality and fault coverage. | 0 | 0.34 | 1981 |
On a relation between algebraic programs and turing machines | 1 | 0.34 | 1977 |