Name
Papers
Collaborators
SHARAD C. SETH
47
51
Citations 
PageRank 
Referers 
671
93.61
1330
Referees 
References 
876
481
Search Limit
1001000
Title
Citations
PageRank
Year
Leverage Redundancy In Hardware Transactional Memory To Improve Cache Reliability00.342018
Exploiting FIFO Scheduler to Improve Parallel Garbage Collection Performance.10.352016
Converting heterogeneous statistical tables on the web to searchable databases.40.432016
SmartStealing: Analysis and Optimization of Work Stealing in Parallel Garbage Collection for Java VM20.372015
Factors affecting scalability of multithreaded Java applications on manycore systems20.372015
Transforming Web Tables to a Relational Database40.422014
End-to-End Conversion of HTML Tables for Populating a Relational Database00.342014
CLU: Co-Optimizing Locality and Utility in Thread-Aware Capacity Management for Shared Last Level Caches80.502014
Locality & utility co-optimization for practical capacity management of shared last level caches50.432012
Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching50.492010
Pvt: Unified Reduction Of Test Power, Volume, And Test Time Using Double-Tree Scan Architecture10.372010
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches180.692010
A novel hybrid delay testing scheme with low test power, volume, and time10.352010
Education00.342009
Comment: projection methods require black border removal.20.392009
Efficient Selection of Observation Points for Functional Tests20.382008
Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid20.372008
Efficient RTL Coverage Metric for Functional Test Selection80.532007
Efficient Test Compaction for Pseudo-Random Testing70.472005
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design60.472005
A Feature-Based Approach To Conflation Of Geospatial Sources522.282004
Low-Energy BIST Design for Scan-based Logic Circuits80.562003
Modeling Fault Coverage of Random Test Patterns90.592003
A Novel Method to Improve the Test Efficiency of VLSI Tests00.342002
Design Verification And Functional Testing Of Finite State Machines00.342001
Adaptive Segmentation of Document Images40.522001
Integrated text and line-art extraction from a topographic map221.072000
Empirical computation of reject ratio in VLSI testing10.341999
Synthesis for Testability by Two-Clock Control30.421997
A Prototype for Adaptive Association of Street Names with Streets on Maps20.351997
Improving Circuit Testability by Clock Control80.641996
HGA: a hardware-based genetic algorithm728.121995
A system for recognizing a large class of engineering drawings361.641995
A switch-level test generation system for synchronous and asynchronous circuits40.401995
Syntactic segmentation and labeling of digitized pages from technical journals755.521993
Clock partitioning for testability120.781993
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits50.911992
A Switch-Level Test Generation System.20.391992
A prototype document image analysis system for technical journals18831.541992
Estimating the Quality of Manufactured Digital Sequential Circuits60.891991
An Experimental Study on Reject Ratio Prediction for VLSI Circuits: Kokomo Revisited358.371990
Testability analysis of synchronous sequential circuits based on structural data1010.331989
A new model for computation of probabilistic testability in combinational circuits264.251989
A fast fault simulation algorithm for combinational circuits103.461988
Predicting Fault Coverage from Probabilistic Testability20.481985
LSI product quality and fault coverage.00.341981
On a relation between algebraic programs and turing machines10.341977