Name
Abstract | ||
|---|---|---|
This paper proposes a new and original FPGA architecturewith testability facilities. It is first demonstrated thatclassical FPGA architectures do not allow to efficientlyimplement sequential circuits with a SCAN chain. It isconsequently proposed to modify the architecture of classicalFPGAs in order to create an Implicit-Scan chain into theFPGA itself called Implicit Scan FPGA (IS-FPGA). Usingthis new FPGA architecture, any sequential circuitimplemented into the FPGA is 'implicitly scanned'. Anoriginal and optimal implementation of the proposedarchitecture is given with minimum area overhead andabsolutely no delay impact. Additionally the technique istransparent for the user as well as for the FPGA mappingtools. Finally, it is demonstrated that the Implicit-Scanconcept allow to over-scan' sequential circuits resulting inhighly testable circuits. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/TEST.2001.966716 | ITC |
Keywords | Field | DocType |
implicit scan,sequential circuit,usingthis new fpga architecture,implicit scan fpga,new symmetric fpga architecture,original fpga architecturewith testability,scan chain,implicit-scan chain,fpga mappingtools,thatclassical fpga architecture,inhighly testable circuit,delay impact,field programmable gate arrays,multiplexing,logic programming,sequential circuits,manufacturing,logic circuits,design for testability | Design for testing,Testability,Logic gate,Sequential logic,Computer science,Field-programmable gate array,Scan chain,FPGA prototype,Electronic engineering,Real-time computing,Reconfigurable computing | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-7171-2 | 23 |
PageRank | References | Authors |
1.53 | 12 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Renovell | 1 | 224 | 18.93 |
| P. Faure | 2 | 23 | 1.53 |
| J. M. Portal | 3 | 176 | 20.95 |
| J. Figueras | 4 | 227 | 19.91 |
| Y. Zorian | 5 | 499 | 47.97 |