Name
Title | ||
|---|---|---|
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/CICC.2011.6055287 | CICC |
Keywords | Field | DocType |
CMOS digital integrated circuits,analogue-digital conversion,delta-sigma modulation,CMOS technology,discrete-time 2-2 MASH ΔΣ ADC,distributed feedback branches,frequency 130 MHz,modulator power consumption,size 0.13 mum,stage-sharing technique,weighted feed-forward summation,ΔΣ modulator,MASH,op-amp sharing,oversampling ratio,stage sharing | Oversampling,Adder,Computer science,Integrator,CMOS,Delta-sigma modulation,Modulation,Electronic engineering,Bandwidth (signal processing),Clock rate | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ramin Zanbaghi | 1 | 19 | 5.18 |
| Saurabh Saxena | 2 | 174 | 16.84 |
| Gabor C. Temes | 3 | 211 | 57.86 |
| Terri S. Fiez | 4 | 167 | 47.25 |