Name
Abstract | ||
|---|---|---|
A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch... |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/4.535410 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Recycling,Latches,CMOS logic circuits,Logic circuits,Circuit noise,CMOS technology,Switches,Energy consumption,Pipelines,Clocks | Journal | 31 |
Issue | ISSN | Citations |
9 | 0018-9200 | 19 |
PageRank | References | Authors |
4.61 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bai-Sun Kong | 1 | 153 | 31.93 |
| Joo-Sun Choi | 2 | 246 | 29.16 |
| Seog-Jun Lee | 3 | 68 | 12.74 |
| Kwyro Lee | 4 | 265 | 70.73 |