| A 2.5–32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE | 0 | 0.34 | 2022 |
| A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis. | 0 | 0.34 | 2018 |
| High-Resolution Synthesized Magnetic Field Focusing for RF Barcode Applications. | 0 | 0.34 | 2018 |
| Corrections to "A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization". | 0 | 0.34 | 2015 |
| A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization | 5 | 0.65 | 2014 |
| 12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels | 6 | 0.90 | 2014 |
| A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique | 15 | 2.21 | 2013 |
| Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than 40dBm. | 0 | 0.34 | 2012 |
| A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts. | 10 | 0.91 | 2012 |
| Hardware-efficient non-decimation RF sampling receiver front-end with reconfigurable FIR filtering. | 0 | 0.34 | 2012 |
| A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology | 6 | 0.60 | 2011 |
| An isolator-less CMOS RF front-end for UHF mobile RFID reader | 4 | 0.96 | 2011 |
| A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner | 27 | 2.65 | 2009 |
| Simple Design of Detector in the Presence of Frequency Offset for IEEE 802.15.4 LR-WPANs | 4 | 0.62 | 2009 |
| Design methodology of baseband analog chain to maximize a spurious free dynamic range for ATSC terrestrial and cable digital TV tuner | 1 | 0.43 | 2008 |
| Continuous Phase Modulation of F-QPSK-B Signals | 4 | 0.72 | 2007 |
| Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL | 7 | 0.64 | 2007 |
| Pseudo Floating Point Representation For Non-Binary Turbo Decoder Extrinsic Information Memory Reduction | 0 | 0.34 | 2007 |
| A 13-dB IIP3 Improved Low-Power CMOS RF Programmable Gain Amplifier Using Differential Circuit Transconductance Linearization for Various Terrestrial Mobile D-TV Applications | 7 | 17.38 | 2006 |
| Low-Power 2.4ghz Cmos Frequency Synthesizer With Differentially Controlled Mos Varactors | 2 | 0.41 | 2006 |
| Effects Of Gradual Enhancement For Receivers At Mobile Terminals In Different Locations With Greedy Scheduling | 1 | 0.47 | 2006 |
| 2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop | 1 | 0.67 | 2006 |
| Efficient probabilistic sphere decoding architecture | 0 | 0.34 | 2006 |
| Cut-Off Rate Of Multiple Antenna Systems Over Frequency-Flat, Fast Fading Channels | 0 | 0.34 | 2006 |
| Probabilistic List Sphere Decoding for LDPC-Coded MIMO-OFDM Systems | 0 | 0.34 | 2006 |
| Capacitive-loaded interstitial antennas for perfect matching and desirable SAR distributions. | 0 | 0.34 | 2006 |
| High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology | 8 | 1.72 | 2005 |
| A 19-Mw 2.6-Mm(2) L1/L2 Dual-Band Cmos Gps Receiver | 27 | 3.45 | 2005 |
| Resistance matrix in crosstalk modeling for multiconductor systems | 1 | 0.40 | 2004 |
| A new measurement technique on inherent-ring-resonance frequency using ring filters | 0 | 0.34 | 2004 |
| Low-power and area-efficient FIR filter implementation suitable for multiple taps | 7 | 0.97 | 2003 |
| A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction | 0 | 0.34 | 2003 |
| An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz | 44 | 9.33 | 2003 |
| Reverse tracing of forward state metric in Log-Map and MAX-Log-MAP decoders | 3 | 0.50 | 2003 |
| Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniques | 2 | 0.46 | 2001 |
| H∞ tuning for task-space feedback control of robot with uncertain Jacobian matrix. | 0 | 0.34 | 2001 |
| Reconfigurable and programmable minimum distance search engine for portable video compression systems | 0 | 0.34 | 2001 |
| Orthogonal transpose-RAM cell array architecture with alternate bit-line to bit-line contact scheme | 0 | 0.34 | 2001 |
| Low-Power 2D Motion Estimation Architecture with Complementary Embedded Memory Banks. | 0 | 0.34 | 2000 |
| Low-power dynamic termination scheme using NMOS diode clamping | 0 | 0.34 | 1999 |
| Implementation And Performance Analysis Of Programmable Test Beds For Real-Time Wireless W-Cdma | 0 | 0.34 | 1999 |
| A design of the new FPGA with data path logic and run time block reconfiguration method | 1 | 0.35 | 1999 |
| A Low-Power Minimum Distance 1d-Search Engine Using Hybrid Digital/Analog Circuit Techniques | 2 | 0.46 | 1999 |
| An 8-Bit-Resolution, 360-Mu S Write Time Nonvolatile Analog Memory Based On Differentially Balanced Constant-Tunneling-Current Scheme (Dbcs) | 6 | 4.00 | 1998 |
| An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS) | 1 | 0.76 | 1998 |
| A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications | 0 | 0.34 | 1997 |
| A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme | 40 | 5.44 | 1997 |
| Charge recycling differential logic (CRDL) for low power application | 19 | 4.61 | 1996 |
| A comparative study on the various monolithic low noise amplifier circuit topologies for RF and microwave applications | 4 | 1.31 | 1996 |
