Name
Abstract | ||
|---|---|---|
Manufacturing test of chips made of multiple IP coresrequires different techniques if ATE is used. As scan chainsare commonly used as access paths to the DUT, ATE architecturesmust be designed to facilitate this arrangement.An increase in ATE performance for scan test requires a reductionin both scan time and memory utilization as commonlyused figures of merit; in this paper, an ATE hardwarearchitecture that allows the scan test to be done inan "interleaved" mode (thus separating the Scan-In andScan-Compare sequences), is utilized together with a noveltest scheduling algorithm. Two variations of the algorithmwhich permit test reordering and merging as well as an efficientgeneration of the so-called monolithic test sequenceare proposed. Scheduling is found in polynomial time complexityand the proposed approach resorts to heuristic conditionsfor merging the vectors. A substantial saving in bothtest time and memory is achieved. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/DELTA.2004.10023 | DELTA |
Keywords | DocType | ISBN |
ate hardwarearchitecture,polynomial time complexityand,proposed approach resort,algorithmwhich permit test reordering,scan-in andscan-compare sequence,ate environment,ip cores,so-called monolithic test sequenceare,ate performance,memory utilization,scan test,bothtest time,access path,merging,polynomial time,figure of merit,scheduling,computational complexity,chip,automatic test equipment | Conference | 0-7695-2081-2 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| L. Schiano | 1 | 53 | 8.35 |
| Y. B. Kim | 2 | 22 | 3.80 |
| F. Lombardi | 3 | 232 | 24.13 |