Name
Abstract | ||
|---|---|---|
ICs with IEEE 1149.1 Boundary Scan (BS) Architecture(a.k.a. JTAG) have been widely used in board level designto increase the testability. An end-to-end test methodologythat utilizes BS architecture for testing boards andsystems throughout the product life cycle is proposed. Theproposed test methodology includes a programmable dynamicBS test architecture and a series of test modulesthat take advantage of the test architecture for completefault coverage. Proposed design-for-testability (DFT)techniques guarantee the co-existence of BS testing withother system functions, such as in-system programming(ISP) and DSP JTAG emulation. At board level, programmabledynamic scan chains are used in a divide-andconquerfashion to increase the flexibility in the developmentphase (or design verification testing (DVT)). Besides,since the DFT techniques are programmable, theycan be used as design-for-diagnosis (DFD) to increase diagnosis resolution during DVT. Address Scan Port (ASP)chips are used to enable multi-drop test bus architecturefor backplane testing as well as system embedded testing.Other advanced techniques, such as analog subsystemtesting and board-level built-in self-test, as well ashow to re-use BS architecture in in-circuit testing (ICT)and manufacture testing are also parts of the proposedmethodology that takes advantage of BS architecture toprovide full scale testing for systems. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/TEST.2000.894252 | ITC |
Keywords | Field | DocType |
boundary scan,in-circuit testing,theproposed test methodology,bs architecture toprovide,system embedded testing,design verification testing,board level,backplane testing,bs testing withother system,end-to-end testing,bs architecture,full scale testing,product life cycle,digital signal processing,chip,functional programming,emulation,divide and conquer,fault coverage,manufacturing,design for testability,dft,in circuit testing,backplanes,system testing,embedded systems,in system programming | Boundary scan,Integration testing,Test Management Approach,System testing,Computer science,Scan chain,Real-time computing,Software performance testing,Electronic engineering,White-box testing,Test compression,Embedded system | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-6546-1 | 2 |
PageRank | References | Authors |
0.51 | 2 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert W. Barr | 1 | 2 | 0.51 |
| Chen-Huan Chiang | 2 | 53 | 7.33 |
| Edward L. Wallace | 3 | 2 | 0.84 |