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CHEN-HUAN CHIANG
Author Info
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Name
Affiliation
Papers
CHEN-HUAN CHIANG
Lucent Technol, Whippany, NJ 07981 USA
11
Collaborators
Citations
PageRank
17
53
7.33
Referers
Referees
References
117
107
80
Search Limit
100
117
Publications (11 rows)
Collaborators (17 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Problems Using Boundary-Scan For Memory Cluster Tests
1
0.37
2008
A New Language Approach For Ijtag
0
0.34
2008
FPGA Prototyping of a Scan Based System-On-Chip Design
3
0.43
2007
Testing and remote field update of distributed base stations in a wireless network
2
0.75
2004
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architecture
8
0.65
2002
BIST TPG for Combinational Cluster Interconnect Testing at Board Level
1
0.42
2000
End-to-End Testing for Boards and Systems Using Boundary Scan
2
0.51
2000
BIST TPG for SRAM cluster interconnect testing at board level
1
0.49
2000
BIST TPG for faults in system backplanes
1
0.46
1997
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan
18
1.14
1997
Random pattern testable logic synthesis
16
1.77
1994
1