Abstract | ||
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Electronic system reliability over soft errors is very critical as the transistor size shrinks. Many recent works have defined the device error rate under radiation for SRAMs in hold mode (static) and during operation (dynamic). This paper evaluates the impact of running test algorithms on SRAMs exposed to neutron radiation in order to define their stressing factor. The results that we show are based on experiments performed at the TSL facility in Uppsala, Sweden using a Quasi-Monoenergetic neutron beam. The evaluation of the test algorithms is based on the calculated device SEU cross section. |
Year | DOI | Venue |
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2012 | 10.1109/IOLTS.2012.6313853 | IOLTS |
Keywords | Field | DocType |
SRAM chips,integrated circuit reliability,integrated circuit testing,neutron effects,radiation hardening (electronics),stress effects,SEU cross section device calculation,SRAM,TSL facility,Uppsala Sweden,device error rate,electronic system reliability,neutron radiation exposure,quasimonoenergetic neutron beam,running test algorithm impact evaluation,single event upset,soft error,test algorithm stress effect evaluation,transistor size shrinking,Cross-section,SRAM,Single Event Upset,neutrons,radiation,test | Neutron,Test algorithm,Computer science,Word error rate,Neutron radiation,Electronic engineering,Static random-access memory,Transistor,Single event upset,Radiation | Conference |
ISSN | Citations | PageRank |
1942-9398 | 0 | 0.34 |
References | Authors | |
1 | 9 |
Name | Order | Citations | PageRank |
---|---|---|---|
G. Tsiligiannis | 1 | 5 | 1.26 |
L. Dilillo | 2 | 44 | 9.49 |
A. Bosio | 3 | 113 | 15.51 |
P. Girard | 4 | 478 | 41.91 |
A. Todri | 5 | 7 | 3.85 |
A. Virazel | 6 | 169 | 23.25 |
Antoine D. Touboul | 7 | 6 | 4.53 |
Frederic Wrobel | 8 | 41 | 11.16 |
F. Saigne | 9 | 11 | 4.89 |