Name
Abstract | ||
|---|---|---|
We introduce the SMTp architecture-an SMT processoraugmented with a coherence protocol thread context,that together with a standard integrated memory controllercan enable the design of (among other possibilities) scalablecache-coherent hardware distributed shared memory(DSM) machines from commodity nodes. We describe theminor changes needed to a conventional out-of-order multi-threadedcore to realize SMTp, discussing issues related toboth deadlock avoidance and performance. We then compareSMTp performance to that of various conventionalDSM machines with normal SMT processors both with andwithout integrated memory controllers. On configurationsfrom 1 to 32 nodes, with 1 to 4 application threads pernode, we find that SMTp delivers performance comparableto, and sometimes better than, machines with more complexintegrated DSM-specific memory controllers. Our resultsalso show that the protocol thread has extremely lowpipeline overhead. Given the simplicity and the flexibility ofthe SMTp mechanism, we argue that next-generation multi-threadedprocessors with integrated memory controllersshould adopt this mechanism as a way of building less complexhigh-performance DSM multiprocessors.
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Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/1028176.1006712 | ACM Sigarch Computer Architecture News |
Keywords | Field | DocType |
flexibility ofthe smtp mechanism,next-generation scalable multi-threading,comparesmtp performance,performance comparableto,coherence protocol thread context,complexintegrated dsm-specific memory controller,complexhigh-performance dsm multiprocessors,smtp architecture-an smt,integrated memory,standard integrated memory,andwithout integrated memory controller,out of order,distributed shared memory,hardware,control systems,cache coherence,sequential consistency,computer architecture,coherence,concurrency control,protocols,multi threading | Multithreading,Computer architecture,Yarn,Concurrency control,Computer science,Parallel computing,Deadlock,Real-time computing,Thread (computing),Distributed shared memory,Memory architecture,Scalability | Conference |
Volume | Issue | ISSN |
32 | 2 | 0163-5964 |
ISBN | Citations | PageRank |
0-7695-2143-6 | 11 | 0.73 |
References | Authors | |
28 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mainak Chaudhuri | 1 | 300 | 18.86 |
| Mark Heinrich | 2 | 11 | 0.73 |