Mainak Chaudhuri - Citegraph

Author Info

Name	Affiliation	Papers
MAINAK CHAUDHURI	Indian Inst Technol, Dept Comp Sci & Engn, Kanpur 208016, Uttar Pradesh, India	34
Collaborators	Citations	PageRank
37	300	18.86
Referers	Referees	References
640	982	717

Search Limit

100982

Publications (34 rows)

Collaborators (37 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Zero Inclusion Victim: Isolating Core Caches from Inclusive Last-level Cache Evictions	0	0.34	2021
Zero Directory Eviction Victim: Unbounded Coherence Directory and Core Cache Isolation	0	0.34	2021
Bandwidth-Aware Last-Level Caching: Efficiently Coordinating Off-Chip Read and Write Bandwidth	0	0.34	2019
Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches.	1	0.35	2017
Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth Sources	1	0.35	2017
Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence Tracking	3	0.38	2017
Sharing-Aware Efficient Private Caching in Many-Core Server Processors	1	0.35	2017
Improving CPU Performance Through Dynamic GPU Access Throttling in CPU-GPU Heterogeneous Processors	3	0.37	2017
Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors.	1	0.37	2017
Divergence Aware Automated Partitioning of OpenCL Workloads.	2	0.36	2016
Accelerating schedule space exploration of multi-threaded programs with GPUs.	0	0.34	2016
Exploiting Dynamic Reuse Probability to Manage Shared Last-level Caches in CPU-GPU Heterogeneous Processors.	3	0.37	2016
Pool directory: Efficient coherence tracking with dynamic directory allocation in many-core systems	3	0.37	2015
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads	11	0.51	2013
Characterizing Multi-Threaded Applications For Designing Sharing-Aware Last-Level Cache Replacement Policies	6	0.41	2013
Performance Evaluation of Concurrent Lock-free Data Structures on GPUs	9	0.61	2012
Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches	23	0.63	2012
Bypass and insertion algorithms for exclusive last-level caches	55	1.31	2011
Improving speculative loop parallelization via selective squash and speculation reuse	0	0.34	2010
Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches	56	2.03	2009
Pagenuca: Selected Policies For Page-Grain Locality Management In Large Shared Chip-Multiprocessor Caches	20	0.80	2009
Implementing a parallel matrix factorization library on the cell broadband engine	4	0.44	2009
Simplifying Active Memory Clusters By Leveraging Directory Protocol Threads	0	0.34	2007
Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors	3	0.40	2007
Long-latency branches: how much do they matter?	0	0.34	2006
Checkpointed Early Load Retirement	41	1.72	2005
Architectural support for uniprocessor and multiprocessor active memory systems	10	0.72	2004
SMTp: An Architecture for Next-generation Scalable Multi-threading	11	0.73	2004
The Impact of Negative Acknowledgments in Shared Memory Scientific Applications	4	0.42	2004
Active memory techniques for ccNUMA multiprocessors	5	0.45	2003
Ocean warning: avoid drowning	6	0.45	2003
Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters	5	0.50	2002
Cache Coherence Protocol Design for Active Memory Systems	4	0.41	2002
Leveraging cache coherence in active memory systems	9	0.64	2002